Semiconductor device

ABSTRACT

To improve reliability of a semiconductor device obtained through a dicing step. In a ring region, a first outer ring is provided outside a seal ring, and a second outer ring is provided outside the first outer ring. This can prevent a crack from reaching even the seal ring that exists in the ring region, for example, when a scribe region located outside the ring region is cut off by a dicing blade.

BACKGROUND

The present invention relates to a semiconductor device and asemiconductor wafer, and to a technology effective in applying to, forexample, a semiconductor device that is provided with a ring region inwhich a seal ring has been arranged outside a circuit region in which anintegrated circuit has been formed and a semiconductor wafer.

Japanese Patent Laid-Open No. 2011-222939 (Patent Document 1) describesa semiconductor device in which a crack protection ring is provided in aregion directly under a crack prevention window located outside amoisture-resistant ring. At this time, a top surface of the crackprotection ring is configured so as to be exposed from a bottom surfaceof the crack prevention window.

Japanese Patent Laid-Open No. 2008-270720 (Patent Document 2) describesa semiconductor device in which a metal wire is provided in a regiondirectly under an opening located outside a moisture-resistant shieldring.

Japanese Patent Laid-Open No. 2011-9795 (Patent Document 3) describes asemiconductor device in which a silicon nitride film peel-off preventiongroove is provided outside a seal ring, being a moisture shielding wall,and in which an external seal ring is provided between the seal ring andthe silicon nitride film peel-off prevention groove.

SUMMARY

For example, there exists a plurality of chip regions in a semiconductorwafer, and these chip regions are partitioned by scribe regions.Additionally, in manufacturing steps of a semiconductor device, the chipregions are separated by dicing the semiconductor wafer along the scriberegions (a dicing step), to produce a plurality of semiconductor chipsfrom the semiconductor wafer.

Here, from a viewpoint of improving reliability of the semiconductorchips obtained through the dicing step, it has been desired to devisestructures of the semiconductor chip and the semiconductor wafer.

The other problems and the new feature will become clear from thedescription of the present specification and the accompanying drawings.

A semiconductor device in one embodiment is provided with: a seal ring;a groove portion formed outside the seal ring; a first outer ringarranged between the seal ring and the groove portion; and a secondouter ring arranged outside the first outer ring, the second outer ringbeing arranged so as to overlap with the groove portion in plan view.

According to one embodiment, reliability of the semiconductor device canbe improved.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a plan view showing a layout configuration of a semiconductorwafer;

FIG. 2 is an enlarged view showing a partial region of the semiconductorwafer shown in FIG. 1;

FIG. 3 is a cross-sectional view taken along a line A-A of FIG. 2;

FIG. 4 is a cross-sectional view schematically showing a step of dicingthe semiconductor wafer;

FIG. 5 is a cross-sectional view explaining a room for improvement in adicing step in a related art;

FIG. 6 is a cross-sectional view showing the room for improvement in thedicing step in which a scribe region is cut off by irradiating thescribe region of the semiconductor wafer with a laser light;

FIG. 7 is an enlarged view showing a partial region of the semiconductorwafer shown in FIG. 1;

FIG. 8 is an enlarged plan view showing a partial region shown in FIG.7, and is the view showing a planar layout configuration near a cornerof a chip region;

FIG. 9 is a cross-sectional view taken along a line A-A of FIG. 7;

FIG. 10 is a cross-sectional view showing a step of dicing asemiconductor wafer in a first embodiment;

FIG. 11 is a cross-sectional view showing a manufacturing step of asemiconductor device in the first embodiment;

FIG. 12 is a cross-sectional view showing a manufacturing step of thesemiconductor device following FIG. 11;

FIG. 13 is a cross-sectional view showing a manufacturing step of thesemiconductor device following FIG. 12;

FIG. 14 is a cross-sectional view showing a manufacturing step of thesemiconductor device following FIG. 13;

FIG. 15 is a cross-sectional view showing a manufacturing step of thesemiconductor device following FIG. 14;

FIG. 16 is a cross-sectional view showing a manufacturing step of thesemiconductor device following FIG. 15;

FIG. 17 is a cross-sectional view showing a manufacturing step of thesemiconductor device following FIG. 16;

FIG. 18 is a cross-sectional view showing a manufacturing step of thesemiconductor device following FIG. 17;

FIG. 19 is a cross-sectional view showing a manufacturing step of thesemiconductor device following FIG. 18;

FIG. 20 is a cross-sectional view showing a manufacturing step of thesemiconductor device following FIG. 19;

FIG. 21 is a cross-sectional view showing a manufacturing step of thesemiconductor device following FIG. 20;

FIG. 22 is a cross-sectional view showing a manufacturing step of thesemiconductor device following FIG. 21;

FIG. 23 is a cross-sectional view showing a manufacturing step of thesemiconductor device following FIG. 22;

FIG. 24 is a cross-sectional view showing a manufacturing step of thesemiconductor device following FIG. 23;

FIG. 25 is a cross-sectional view showing a manufacturing step of thesemiconductor device following FIG. 24;

FIG. 26 is a cross-sectional view showing a configuration of asemiconductor wafer in a second embodiment;

FIG. 27 is a cross-sectional view showing a configuration of asemiconductor wafer in a third embodiment;

FIG. 28 is a cross-sectional view showing a configuration of asemiconductor wafer in a fourth embodiment;

FIG. 29 is a cross-sectional view showing a configuration of asemiconductor wafer in a fifth embodiment;

FIG. 30 is a cross-sectional view showing a configuration of asemiconductor wafer in a sixth embodiment;

FIG. 31 is a view showing a planar layout configuration near a corner ofa chip region in a semiconductor wafer of a seventh embodiment;

FIG. 32 is a cross-sectional view taken along a line A-A of FIG. 31;

FIG. 33 is a cross-sectional view taken along a line B-B of FIG. 31;

FIG. 34 is a view showing a planar layout configuration near a corner ofa chip region in a semiconductor wafer of an eighth embodiment;

FIG. 35 is a cross-sectional view taken along a line A-A of FIG. 34;

FIG. 36 is a cross-sectional view taken along a line B-B of FIG. 34;

FIG. 37 is a view showing a planar layout configuration near a corner ofa chip region in a semiconductor wafer of a ninth embodiment;

FIG. 38 is a cross-sectional view taken along a line A-A of FIG. 37;

FIG. 39 is a view showing a planar layout configuration near a corner ina semiconductor wafer of a tenth embodiment; and

FIG. 40 is a cross-sectional view taken along a line A-A of FIG. 39.

DETAILED DESCRIPTION

The following embodiments will be explained, divided into pluralsections or embodiments, if necessary for convenience. Except for thecase where it shows clearly in particular, they are not mutuallyunrelated and one has relationships such as a modification, details, andsupplementary explanation of some or entire of another.

In the following embodiments, when referring to the number of elementsor the like (including the number, a numeric value, an amount, a rangeand the like), they may be not restricted to the specific number but maybe greater or smaller than the specific number, except for the casewhere they are clearly specified in particular and where they areclearly restricted to a specific number theoretically.

Furthermore, in the following embodiments, it is needless to say that anelement (including an element step and the like) is not necessarilyindispensable, except for the case where it is clearly specified inparticular and where it is considered to be clearly indispensable from atheoretical point of view or the like.

Similarly, in the following embodiments, when shape, positionrelationship or the like of an element or the like is referred to, whatresembles or is similar to the shape substantially shall be included,except for the case where it is clearly specified in particular andwhere it is considered to be clearly not right from a theoretical pointof view. This statement also applies to the numeric value and rangedescribed above.

In all the drawings for explaining embodiments, the same symbol isattached to the same member, as a principle, and the repeatedexplanation thereof is omitted. In order to make a drawing intelligible,hatching may be attached even if it is a plan view.

First Embodiment

FIG. 1 is a plan view showing a layout configuration of a semiconductorwafer WF. As shown in FIG. 1, the semiconductor wafer WF issubstantially disk-shaped, and has a plurality of chip regions CR in aninner region. An integrated circuit including a semiconductor element,such as an MISFET (Metal Insulator Semiconductor Field EffectTransistor), and a wiring is formed in each of the chip regions CR, andthese chip regions CR are partitioned by a scribe region SCR.Additionally, in manufacturing steps of a semiconductor device, the chipregions CR are cut off by dicing the semiconductor wafer WF along thescribe region SCR, to produce a plurality of semiconductor chips fromthe semiconductor wafer WF.

A technical idea in the present first embodiment has been thought out inorder to prevent decrease in reliability of a semiconductor device(semiconductor chip) due to a crack with the risk of occurrence indicing the semiconductor wafer WF. Hereinafter, a related art will befirst explained, and a room for improvement existing in the related artwill be explained, and after that, the technical idea in the presentfirst embodiment which has been devised to improve the related art willbe explained.

<Explanation of related art> FIG. 2 is an enlarged view showing apartial region of the semiconductor wafer WF shown in FIG. 1.Specifically, FIG. 2 shows the enlarged view of the region surroundedwith a dashed line of FIG. 1. In FIG. 2, it can be seen that four chipregions CR are shown, and that a scribe region SCR is formed so as topartition these four chip regions CR. Additionally, the four chipregions CR shown in FIG. 2 are separated into mutually independent foursemiconductor chips, by dicing the semiconductor wafer WF along thescribe region SCR.

FIG. 3 is a cross-sectional view taken along a line A-A of FIG. 2. Asshown in FIG. 3, the scribe region SCR is formed outside the chip regionCR, and this chip region CR is, for example, configured to include acircuit region LR in which an integrated circuit has been formed and aring region RR formed outside the circuit region LR. Here, among the tworegions partitioned by a boundary line, a region side away from a centerof the individual chip region CR is defined as an “outside”, and aregion side near the center of the individual chip region CR is definedas an “inside”. Namely, in a certain cross section of the semiconductorchip, the region side near an outer periphery of the semiconductor chip,which is a cut surface of the semiconductor chip, is defined as the“outside”, and the region side away from the outer periphery of thesemiconductor chip is defined as the “inside”.

In the circuit region LR shown in FIG. 3, a field insulating film STI isformed on a semiconductor substrate 1S and, for example, a field effecttransistor TR is formed in an active region partitioned by the fieldinsulating film STI. Additionally, a multi-layered interlayer insulatingfilm is formed so as to cover the field effect transistor TR, and plugsPLG1 connected to the field effect transistor TR, and wirings WL1electrically connected to the plugs PLG1 are formed in the interlayerinsulating film. The wiring WL1, for example, includes a copper wiring,and is formed in the interlayer insulating film in a multi-layeredmanner. For example, a pad PD including an aluminum film is formed overthe wiring WL1 formed in a top layer, and a surface protection film PASis formed so as to cover the pad PD. Additionally, an opening is formedin the surface protection film PAS, and a part of the pad PD is exposedfrom the opening. A wire including a metal line is connected to theexposed pad PD, for example, in a wire bonding step.

Subsequently, a seal ring SR is formed in the ring region RR shown inFIG. 3 so as to be connected to the semiconductor substrate 1S. The sealring SR, for example, includes plugs PLG2 connected to the semiconductorsubstrate 1S, and metal patterns MP1 connected to the plugs PLG2. Thatis, the interlayer insulating film is formed over the semiconductorsubstrate 1S also in the ring region RR, the plugs PLG2 and themulti-layered metal patterns MP1 are formed in the interlayer insulatingfilm, and the metal patterns MP1 adjacent to each other in a laminationdirection are connected with the plugs.

The metal pattern MP1 is, for example, formed from a copper pattern and,for example, a metal pattern AMP including an aluminum film is formedover the metal pattern MP1 in the top layer. The seal ring SR configuredas described above includes: the plugs PLG2; the multi-layered metalpatterns MP1; the plugs that couple the metal patterns to each other;and the metal pattern AMP, and configures a kind of protection barrier.Accordingly, moisture entering from an outside of the ring region RR issuppressed from entering the circuit region LR by the seal ring SR thatfunctions as the protection barrier. Namely, the seal ring SR formed inthe ring region RR has a function to prevent entering of the moisturefrom the outside to the circuit region LR. Thereby, according to therelated art, since entering of the moisture to the circuit region LR canbe suppressed by the seal ring SR formed in the ring region RR,reliability of the semiconductor device (semiconductor chip) can beimproved.

Furthermore, in the related art, as shown in FIG. 3, the surfaceprotection film PAS is formed over the interlayer insulating filmincluding a portion over the seal ring SR, and a groove portion DIT thatreaches the interlayer insulating film is formed in the surfaceprotection film PAS. Namely, in the related art, the groove portion DITis formed outside the seal ring SR in FIG. 3. Additionally, the scriberegion SCR is formed outside the ring region RR in which the seal ringSR and the groove portion DIT have been formed.

In the scribe region SCR shown in FIG. 3, the interlayer insulating filmis formed over the semiconductor substrate 1S, and the surfaceprotection film PAS is formed over this interlayer insulating film. Itis to be noted that, for example, a TEG pattern may be formed in thescribe region SCR. The TEG pattern means the pattern including anexperimental sample fabricated to evaluate a fundamental structure, aphysical property, an electrical characteristic, circuit operation,reliability, a yield, and the like in an element level or an IC(Integrated Circuit) level. However, illustration of the TEG patternformed in the scribe region SCR is omitted in the present specification.

The related art is configured as described above and hereinafter,particularly, a function of the groove portion DIT formed in the ringregion RR will be explained. FIG. 4 is a cross-sectional viewschematically showing a step of dicing the semiconductor wafer. In FIG.4, the scribe region SCR is cut off by a dicing blade DB in the dicingstep.

At this time, the dicing blade DB rotatingly cuts off the scribe regionSCR, and a downward force is applied to the semiconductor wafer when therotating dicing blade DB enters the semiconductor wafer, and an upwardforce is applied to the semiconductor wafer when the rotating dicingblade DB gets out of the semiconductor wafer.

For this reason, since the force is applied to the semiconductor waferin the scribe region SCR of the semiconductor wafer being cut off by thedicing blade DB, the semiconductor wafer may have a crack.

In a manner described above, it is conceived that when the crack occursin the scribe region SCR, the crack reaches from the scribe region SCRto the ring region RR, and even to the seal ring SR formed in the ringregion RR. In this case, the seal ring SR may be destroyed, and when itis destroyed, it becomes impossible to prevent moisture from enteringthe circuit region LR. As a result of this, there is concern overcausing failure of the integrated circuit formed in the circuit regionLR.

Consequently, the groove portion DIT is provided in the ring region RRin the related art. Specifically, the groove portion DIT is providedoutside the seal ring SR formed in the ring region RR. In this case, forexample, as shown in FIG. 4, a crack CLK1 occurring in the dicing stepis formed so as to extend to a scribe region SCR side with a bottom ofthe groove portion DIT being as a starting point. The reason is thatsince the groove portion DIT is formed by removing the surfaceprotection film PAS, a thickness of the semiconductor wafer is thin andthe semiconductor wafer is easily broken in the groove portion DIT. Thatis, in the related art, an easily broken portion is intentionally formedby providing the groove portion DIT in the surface protection film PAS.Thereby, it is conceived that the crack CLK1 occurring in the dicingstep may be made with the easily broken bottom of the groove portion DITbeing as the starting point, and in this case, the crack CLK1 does notreach the seal ring SR as shown in FIG. 4. From this, according to therelated art, it is conceived that the seal ring SR can be protected fromthe crack CLK1 occurring in the dicing step.

However, as a result of examination of the above-mentioned related artby the present inventor, it became obvious that there exists a room forfurther improvement. Hereinafter, the room for improvement existing inthe related art will be explained.

<Room for improvement existing in related art> FIG. 5 is across-sectional view explaining the room for improvement in the dicingstep in the related art. As shown in FIG. 5, for example, in the scriberegion SCR being cut off by the dicing blade DB, a force is applied tothe semiconductor wafer. At this time, in the related art, the grooveportion DIT is provided outside the seal ring SR formed in the ringregion RR.

In this case, for example, as shown in FIG. 5, it is conceived that acrack CLK2 occurring in the dicing step may occur with the bottom of thegroove portion DIT being as a starting point in many cases, the bottombeing intentionally formed so as to be easily broken.

However, there is conceived not only a case where the crack CLK2 havingoccurred with the bottom of the groove portion DIT being as the startingpoint progresses toward the scribe region SCR outside the ring regionRR, but a case where it progresses toward the seal ring SR arrangedinside the groove portion DIT. That is, even though the easily brokengroove portion DIT is intentionally provided, a progressing direction ofthe crack CLK2 having occurred at the bottom of the groove portion DITcannot be controlled.

Accordingly, for example, as shown in FIG. 4, when the crack CLK1 havingoccurred at the bottom of the groove portion DIT progresses toward thescribe region SCR, the crack CLK1 can be prevented from reaching theseal ring SR.

Meanwhile, for example, as shown in FIG. 5, when the crack CLK2 havingoccurred at the bottom of the groove portion DIT progresses toward theseal ring SR, the crack CLK2 reaches the seal ring SR, and the seal ringSR may be destroyed.

Furthermore, when the force (stress) applied to the semiconductor waferin the dicing step is too strong, for example, as shown in FIG. 5, thereis a case where the bottom of the groove portion DIT may not serve asthe starting point of occurrence of a crack CLK3, but a contact regionof the dicing blade DB and the semiconductor wafer may serve as thestarting point. In this case, the crack CLK3 progresses toward the sealring SR, the crack CLK3 reaches the seal ring SR, and the seal ring SRmay be destroyed.

From the discussion described above, in the related art, the crackhaving occurred in the dicing step cannot be fully prevented fromreaching the seal ring SR formed in the ring region RR, and as a resultof this, there exists a room for improvement that moisture cannot bereliably prevented from entering the circuit region LR due todestruction of the seal ring SR by the crack. Namely, there exists theroom for improvement in the related art from a viewpoint of improvingreliability of the semiconductor device.

Here, for example, it is conceived that a distance L1 between the sealring SR and the groove portion DIT is made larger in FIG. 5. The reasonis that the crack CLK2 occurs with the groove portion DIT being as thestarting point by increasing the distance L1 between the seal ring SRand the groove portion DIT, and that even when the crack CLK2 progressestoward the seal ring SR, a possibility of the crack CLK2 reaching theseal ring SR can be made lower.

Furthermore, for example, as shown in FIG. 5, it is conceived that evenwhen the bottom of the groove portion DIT does not serve as the startingpoint of occurrence of the crack CLK3, but the contact region of thedicing blade DB and the semiconductor wafer serves as the startingpoint, a distance from the starting point of the crack CLK3 to the sealring SR is large, and thus a possibility of the crack CLK3 reaching theseal ring SR can be made lower.

However, since increasing the distance L1 between the seal ring SR andthe groove portion DIT means increasing a size of the ring region RR,and the ring region RR constitutes a part of the chip region CR,increase of the ring region RR means increase of the chip region CR.From this, the number of the semiconductor chips obtained from a singlesemiconductor wafer decreases, and thereby manufacturing cost of asemiconductor device rises.

As described above, it is conceived that a configuration for increasingthe distance L1 between the seal ring SR and the groove portion DIT isthe useful configuration from a viewpoint that possibilities of thecracks CLK2 and CLK3 reaching the seal ring SR can be made lower.However, when sizes of the cracks CLK2 and CLK3 are large, there existsa potential of the seal ring SR being destroyed even though the distanceL1 between the seal ring SR and the groove portion DIT is increased, andthus it is conceived that increasing the distance L1 cannot be said tobe a sufficient measure from a viewpoint of reliably preventingdestruction of the seal ring SR. Furthermore, as mentioned above, whenthe configuration for increasing the distance L1 between the seal ringSR and the groove portion DIT is employed, increase of a size of thechip region CR including the ring region RR is inevitably caused, and itis conceived that the configuration cannot be said to bean effectivemeasure also from a viewpoint of reducing the manufacturing cost of thesemiconductor device.

In addition, in the dicing step, there also exists a technology (laserdicing) of cutting the semiconductor wafer by irradiating the scriberegion SCR with a laser light LAR, for example, as shown in FIG. 6, inaddition to a method for cutting the semiconductor wafer using thedicing blade DB, for example, as shown in FIGS. 4 and 5.

FIG. 6 is a cross-sectional view showing a room for improvement in thedicing step in which the scribe region SCR is cut by irradiating thescribe region SCR of the semiconductor wafer with the laser light LAR.In FIG. 6, a technology called laser dicing is the technology in whichthe semiconductor wafer is irradiated with the laser light LAR to heatan irradiation region, and thereby the irradiation region of thesemiconductor wafer is burned to be cut off. In this case, since notonly the region irradiated with the laser light LAR but a peripheralregion of the irradiation region is heated, a film burns and disappearsalso in the peripheral region. At this time, flammability of the filmdiffers due to a film type formed at the semiconductor wafer, andheating distribution. From this, for example, as shown in FIG. 6, a cutsurface by laser dicing is likely to be a concavo-convex shape due to adifference in flammability of the film formed at the semiconductorwafer. As a result of this, foreign substances (dust) easily occur(s)from the concavo-convex shaped cut surface.

Particularly, in recent years, for example, a low-dielectric film whosedielectric constant is lower than a silicon oxide film typified by anSiOC film may be used for the interlayer insulating film in order toreduce a parasitic capacitance of the interlayer insulating film. Forexample, in a case of the SiOC film, the interlayer insulating film iseasy to burn since it includes carbon. Accordingly, it is conceived thatwhen the low-dielectric film is used for a part of the interlayerinsulating film, there is a remarkable difference inflammability of thefilm formed over the semiconductor wafer, and as a result,convexoconcave of the cut surface by the laser dicing becomesremarkable.

From the discussion described above, it can be seen that there existsthe room for improvement in the related art in structures of thesemiconductor chip and the semiconductor wafer from a viewpoint ofimproving reliability of the semiconductor chip obtained through thedicing step. Consequently, devising in the room for improvement thatexists in the above-mentioned related art is made in the present firstembodiment. Hereinafter, there will be explained the technical idea inthe present first embodiment in which the devising has been made.

<Configuration of semiconductor device in First Embodiment> FIG. 7 is anenlarged view showing a partial region of the semiconductor wafer WFshown in FIG. 1. Specifically, FIG. 7 shows an enlarged view of a regionsurrounded with a dashed line of FIG. 1. In FIG. 7, it can be seen thatfour chip regions CR are shown, and that the scribe region SCR is formedso as to partition these four chip regions CR. Additionally, the fourchip regions CR shown in FIG. 7 are separated into mutually independentfour semiconductor chips by dicing the semiconductor wafer WF along thescribe region SCR.

FIG. 8 is an enlarged plan view showing a region AR shown in FIG. 7, andis the view showing a planar layout configuration near a corner CNR of achip region CR. As shown in FIG. 8, the seal ring SR is formed in thechip region CR having the corner CNR. This seal ring SR is arranged soas to extend along an outer peripheral line of the chip region CR in aregion other than the corner CNR, and it is arranged so as to be spacedapart from the corner CNR in the corner CNR. Namely, the seal ring SRis, as shown in FIG. 8, arranged so that a distance between the cornerCNR and the seal ring SR is larger than a distance between the outerperipheral line of the chip region CR in the region other than thecorner CNR and the seal ring SR.

Here, in the present specification, an arrangement configuration of theseal ring SR in the corner CNR is referred to as an inclined pattern.There will be explained a reason hereinafter that the seal ring SR hasthe inclined pattern in the corner CNR of the chip region CR. Namely, acrack easily occurs in the corner CNR of the chip region CR comparedwith an outer peripheral region other than the corner CNR. Particularly,a crack easily occurs that goes to an inside of the chip region CR fromthe corner CNR. In this case, for example, when the distance between thecorner CNR and the seal ring SR is small, a crack having occurred at thecorner CNR easily reaches the seal ring SR. As a result of this, theseal ring SR is destroyed by the crack, and the seal ring SR does notfulfill a function as a moisture protection barrier. Thereby, moisturealso enters the circuit region, which is an inner region of the sealring SR, which exerts a harmful influence on operational reliability ofthe integrated circuit formed in the circuit region.

From this, it is configured such that the seal ring SR has the inclinedpattern in the corner CNR of the chip region CR in the present firstembodiment. In this case, since the distance between the corner CNR andthe seal ring SR is large, a crack can be suppressed from reaching eventhe seal ring SR even though the crack occurs at the corner CNR andprogresses in an inner direction of the chip region CR. As a result ofthis, even if the crack occurs at the corner CNR in which the crackeasily occurs, a potential of the seal ring SR being destroyed by thecrack can be reduced. Namely, since the function of the seal ring SR asthe moisture protection barrier can be maintained even if the crackoccurs at the corner CNR, moisture can be prevented from entering eventhe circuit region, which is the inner region of the seal ring SR.Thereby, the operational reliability of the integrated circuit formed inthe circuit region can be improved.

Subsequently, in the present first embodiment, the groove portion (slit)DIT is arranged along the outer peripheral line of the chip region CR.Specifically, as shown in FIG. 8, the groove portion DIT extends alongthe outer peripheral line of the chip region CR including the cornerCNR. At this time, the groove portion DIT is arranged outside the sealring SR in plan view. That is, the groove portion DIT is arranged so asto be sandwiched between the outer peripheral line of the chip region CRand the seal ring SR in plan view.

Additionally, in the present first embodiment, in plan view, an outerring OUR1 is provided between the groove portion DIT and the seal ringSR, and the outer ring OUR1 also extends along the outer peripheral lineof the chip region CR. Furthermore, in the present first embodiment, anouter ring OUR2 is provided outside the outer ring OUR1, and the outerring OUR2 also extends along the outer peripheral line of the chipregion CR. Particularly, the outer ring OUR2 is arranged so as tooverlap with the groove portion DIT in plan view.

Here, as shown in FIG. 8, a width W1 of the seal ring SR is larger thana width W2 of the outer ring OUR1 and a width W3 of the outer ring OUR2,and the width W2 of the outer ring OUR1 and the width W3 of the outerring OUR2 are the same as each other. In other words, the width W2 ofthe outer ring OUR1 and the width W3 of the outer ring OUR2 are smallerthan the width W1 of the seal ring SR. Although in the present firstembodiment, the width W2 of the outer ring OUR1 and the width W3 of theouter ring OUR2 are set to be the same as each other, most suitablewidths can be appropriately selected as the width W2 of the outer ringOUR1 and the width W3 of the outer ring OUR2 as long as they are smallerthan the width W1 of the seal ring SR.

In addition, in the region other than the corner CNR, a distance X1between the seal ring SR and the outer ring OUR1 is larger than adistance X2 between the outer ring OUR1 and the outer ring OUR2. Inother words, the distance X2 between the outer ring OUR1 and the outerring OUR2 is smaller than the distance X1 between the seal ring SR andthe outer ring OUR1.

Similarly, also in the corner CNR, a distance Y1 between the seal ringSR and the outer ring OUR1 is larger than a distance Y2 between theouter ring OUR1 and the outer ring OUR2. In other words, the distance Y2between the outer ring OUR1 and the outer ring OUR2 is smaller than thedistance Y1 between the seal ring SR and the outer ring OUR1.

At this time, the distance X1 and the distance Y1 between the seal ringSR and the outer ring OUR1 are a distance between an outer peripheralline of the seal ring SR and an inner peripheral line of the outer ringOUR1, and the distance X2 and the distance Y2 between the outer ringOUR1 and the outer ring OUR2 are a distance between an outer peripheralline of the outer ring OUR1 and an inner peripheral line of the outerring OUR2.

Next, FIG. 9 is a cross-sectional view taken along a line A-A of FIG. 7.As shown in FIG. 9, the scribe region SCR is formed in an outer regionof the chip region CR, and this chip region CR is, for example,configured so as to include the circuit region LR in which theintegrated circuit has been formed, and the ring region RR formedoutside the circuit region LR.

In the circuit region LR shown in FIG. 9, the field insulating film STIis formed on the semiconductor substrate 1S and, for example, the fieldeffect transistor TR is formed in the active region partitioned by thefield insulating film STI. Additionally, the multi-layered interlayerinsulating film is formed so as to cover the field effect transistor TR,and the plugs PLG1 connected to the field effect transistor TR, and thewirings WL1 electrically connected to the plugs PLG1 are formed in thisinterlayer insulating film. This wiring WL1, for example, includes thecopper wiring, and is formed in the interlayer insulating film in themulti-layered manner. For example, the pad PD including the aluminumfilm is formed over the wiring WL1 formed in the top layer, and thesurface protection film PAS is formed so as to cover the pad PD.Additionally, the opening is formed in the surface protection film PAS,and the part of the pad PD is exposed from this opening. The wireincluding metal is connected to the exposed pad PD, for example, in awire bonding step.

Subsequently, the seal ring SR is formed in the ring region RR shown inFIG. 9 so as to be connected to the semiconductor substrate 1S. Thisseal ring SR, for example, includes plugs PLG2 connected to thesemiconductor substrate 1S, and metal patterns MP1 connected to theplugs PLG2. That is, the interlayer insulating film is formed over thesemiconductor substrate 1S also in the ring region RR, the plugs PLG2and the multi-layered metal pattern MP1 are formed in this interlayerinsulating film, and the metal patterns MP1 adjacent to each other inthe lamination direction are connected with the plugs.

The metal pattern MP1 is, for example, formed from the copper patternand, for example, a metal pattern AMP including the aluminum film isformed over the metal pattern MP1 of the top layer. The seal ring SRconfigured as described above includes: the plugs PLG2; themulti-layered metal pattern MP1; the plugs that couple the metalpatterns to each other; and the metal pattern AMP, and constitutes akind of protection barrier. Accordingly, moisture entering from theoutside of the ring region RR is suppressed from entering the circuitregion LR by the seal ring SR that functions as the protection barrier.Namely, the seal ring SR formed in the ring region RR has the functionto prevent entering of the moisture from the outside to the circuitregion LR. Thereby, according to the present first embodiment, sinceentering of the moisture to the circuit region LR can be suppressed bythe seal ring SR formed in the ring region RR, reliability of thesemiconductor device (semiconductor chip) can be improved.

Furthermore, in the present first embodiment, as shown in FIG. 9, thesurface protection film PAS is formed over the interlayer insulatingfilm including the portion over the seal ring SR, and the groove portionDIT that reaches the interlayer insulating film is formed in the surfaceprotection film PAS. Namely, in the present first embodiment, the grooveportion DIT is formed outside the seal ring SR in plan view from above amain surface side of the semiconductor substrate 1S (refer to FIG. 8).

In addition, in the present first embodiment, as shown in FIG. 9, theouter ring OUR1 is formed outside the seal ring SR, and the outer ringOUR2 is formed outside this outer ring OUR1. In detail, in plan viewfrom above the main surface side of the semiconductor substrate 1S, theouter ring OUR1 is arranged between the seal ring SR and the grooveportion DIT, and the outer ring OUR2 is arranged so as to overlap withthe groove portion DIT (refer to FIG. 8). These outer rings OUR1 andOUR2 are, as shown in FIG. 9, arranged above the field insulating filmSTI, and are arranged spaced apart from the field insulating film STI.Namely, the outer ring OUR1 and the outer ring OUR2 are not connected tothe field insulating film STI with a plug.

Additionally, the outer ring OUR1 includes the metal pattern MP2.Namely, the field insulating film STI is formed on the semiconductorsubstrate 1S, and the interlayer insulating film is formed over thefield insulating film STI. Additionally, the multi-layered metal patternMP2 is formed in the interlayer insulating film, and the metal patternsMP2 adjacent to each other in the lamination direction are connectedwith the plugs. Similarly, the outer ring OUR2 includes the metalpattern MP3. Namely, the field insulating film STI is formed on thesemiconductor substrate 1S, and the interlayer insulating film is formedover the field insulating film STI. Additionally, the multi-layeredmetal pattern MP3 is formed in the interlayer insulating film, and themetal patterns MP3 adjacent to each other in the lamination directionare connected with plugs. As described above, the outer ring OUR1includes a laminated structure including the plurality of metal patternsMP2 arranged in a laminated manner so as to overlap with each other inplan view, and the plurality of plugs that mutually connects the metalpatterns MP2 adjacent to each other in the lamination direction.Similarly, the outer ring OUR2 includes a laminated structure includingthe plurality of metal patterns MP3 arranged in a laminated manner so asto overlap with each other in plan view, and the plurality of plugs thatmutually connects the metal patterns MP3 adjacent to each other in thelamination direction.

Next, as shown in FIG. 9, the scribe region SCR is formed outside thering region RR in which the seal ring SR, the groove portion DIT, theouter ring OUR1, and the outer ring OUR2 have been formed.

In the scribe region SCR shown in FIG. 9, the field insulating film STIis formed over the semiconductor substrate 1S, and the interlayerinsulating film is formed over the field insulating film STI. Thesurface protection film PAS is formed over this interlayer insulatingfilm. It is to be noted that although, for example, a TEG pattern may beformed in the scribe region SCR, illustration of the TEG pattern isomitted in the present first embodiment.

<Features in First Embodiment> The semiconductor wafer (semiconductordevice) in the present first embodiment is configured as describedabove, and feature points thereof will be explained hereinafter. A firstfeature point of the present first embodiment lies in the point that inthe ring region RR, the outer ring OUR1 is provided outside the sealring SR, and the outer ring OUR2 is provided outside the outer ringOUR1.

Thereby, for example, when the scribe region SCR located outside thering region RR is cut by a dicing blade, a crack can be prevented fromreaching even the seal ring SR that exists in the ring region RR. Thatis, in the present first embodiment, since the outer rings OUR1 and OUR2are provided outside the seal ring SR, the crack reaches the outer ringOUR1 or the outer ring OUR2 before reaching the seal ring SR, and stopsthere. As a result of this, according to the present first embodiment, acrack occurring in the dicing step can be prevented from reaching eventhe seal ring SR that exists in the ring region RR.

Hereinafter, this point will be explained in detail. FIG. 10 is across-sectional view showing a step of dicing the semiconductor wafer inthe present first embodiment. In FIG. 10, shown is a state where thescribe region SCR is cut by the rotating dicing blade DB.

In FIG. 10, for example, when the scribe region SCR is cut by the dicingblade DB, a force is applied to the semiconductor wafer. At this time,in the semiconductor wafer in the present first embodiment, the grooveportion DIT is provided outside the seal ring SR formed in the ringregion RR. In this case, for example, as shown in FIG. 10, it isconceived that the crack CLK2 occurring in the dicing step may usuallyoccur with the bottom of the groove portion DIT being as the startingpoint, the bottom being intentionally formed so as to be easily broken.

However, there is conceived not only a case where the crack CLK2 havingoccurred with the bottom of the groove portion DIT being as the startingpoint progresses toward the scribe region SCR outside the ring regionRR, but a case where it progresses toward the seal ring SR arrangedinside the groove portion DIT. That is, even though the easily brokengroove portion DIT is intentionally provided, the progressing directionof the crack CLK2 having occurred at the bottom of the groove portionDIT cannot be controlled. As a result of this, as shown in FIG. 10,there is conceived the case where the crack CLK2 having occurred at thebottom of the groove portion DIT progresses toward the seal ring SR.

On this point, the outer ring OUR1 is provided between the seal ring SRand the groove portion DIT in the present first embodiment. For thisreason, even if, as shown in FIG. 10, the crack CLK2 having occurred atthe bottom of the groove portion DIT progresses toward the seal ring SR,the crack CLK2 inevitably reaches the outer ring OUR1 before reachingthe seal ring SR. Namely, in the present first embodiment, the outerring OUR1 is provided in an inner region closer to a seal ring SR sidethan the groove portion DIT. Thereby, progress of the crack CLK2 stopsat a stage of having reached the outer ring OUR1.

That is, according to the present first embodiment, even though thecrack CLK2 with the bottom of the groove portion DIT being as thestarting point progresses to the seal ring SR side, the bottom beingintentionally formed so as to be easily broken, the crack stops at theouter ring OUR1 serving as a barrier before reaching the seal ring SR.For this reason, destruction of the seal ring SR by the crack CLK2 canbe prevented.

Accordingly, according to the present first embodiment, destruction ofthe seal ring SR due to the crack CLK2 can be effectively prevented byproviding the outer ring OUR1 between the seal ring SR and the grooveportion DIT. As a result of this, according to the present firstembodiment, entering of moisture to the circuit region LR due todestruction of the seal ring SR by the crack CLK2 can be reliablyprevented, and thereby reliability of the semiconductor wafer and thesemiconductor chip (semiconductor device) obtained by dicing thesemiconductor wafer can be improved.

As described above, in the present first embodiment, the feature lies inthe point that the outer ring OUR1 is provided outside the seal ring SRand inside the groove portion DIT. For example, when the outer ring OUR1is formed outside the groove portion DIT even though the outer ring OUR1is formed outside the seal ring SR, the outer ring OUR1 does not becomeany barrier with respect to the crack CLK2 that progresses to the sealring SR side with the bottom of the groove portion DIT being as thestarting point. In contrast with this, as in the present firstembodiment, precisely because the outer ring OUR1 is located outside theseal ring SR, and is formed inside the groove portion DIT, the outerring OUR1 functions as the barrier to stop the progress of the crackCLK2 to the seal ring SR with respect to the crack CLK2 that progressesto the seal ring SR side with the bottom of the groove portion DIT beingas the starting point. Namely, destruction of the seal ring SR due tothe crack CLK2 reaching the seal ring SR can be prevented only byproviding the outer ring OUR1 outside the seal ring SR and inside thegroove portion DIT.

Subsequently, in the present first embodiment, the outer ring OUR2 isprovided outside the outer ring OUR1 so as to overlap with the grooveportion DIT in plan view. Thereby, advantages shown hereinafter can alsobe obtained. Namely, when the force (stress) applied to thesemiconductor wafer in the dicing step is too strong, for example, asshown in FIG. 10, there is a case where the bottom of the groove portionDIT may not serve as the starting point of occurrence of a crack CLK3,but a contact region of the dicing blade DB and the semiconductor wafermay serve as the starting point. In this case, the crack CLK3 progressestoward the seal ring SR, and when the crack CLK3 reaches the seal ringSR, the seal ring SR may be destroyed.

On this point, the outer ring OUR2 is provided outside the outer ringOUR1 in the present first embodiment. For this reason, even if, as shownin FIG. 10, the crack CLK3 with the contact region of the dicing bladeDB and the semiconductor wafer being as a starting point occurs, thecrack CLK3 inevitably reaches the outer ring OUR2 before reaching theseal ring SR. Namely, the outer ring OUR2 is provided outside the sealring in the present first embodiment. Thereby, progress of the crackCLK3 stops at a stage of having reached the outer ring OUR2.

Accordingly, according to the present first embodiment, destruction ofthe seal ring SR due to the crack CLK3 can be effectively prevented byproviding the outer ring OUR2 outside the seal ring SR. As a result ofthis, according to the present first embodiment, entering of moisture tothe circuit region LR due to destruction of the seal ring SR by thecrack CLK3 can be reliably prevented, and thereby reliability of thesemiconductor wafer and the semiconductor chip (semiconductor device)obtained by dicing the semiconductor wafer can be improved.

Here, a main reason that the outer ring OUR1 is provided outside theseal ring SR and inside the groove portion DIT is to prevent fromreaching even the seal ring SR the crack CLK2 that progresses to theseal ring SR side with the bottom of the groove portion DIT being as thestarting point. Furthermore, it is conceived that the outer ring OUR1also has a function to prevent the progress of the crack CLK3 to theseal ring SR side even if the crack CLK3 with the contact region of thedicing blade DB and the semiconductor wafer being as the starting point.That is, it can be conceived that as long as the outer ring OUR1 isprovided, there is no need to provide the outer ring OUR2.

However, the outer ring OUR2 is provided outside the outer ring OUR1 inthe present first embodiment. Hereinafter, this reason will beexplained. For example, when the force (stress) applied to thesemiconductor wafer in the dicing step is too strong, there is the casewhere the bottom of the groove portion DIT may not serve as the startingpoint of occurrence of the crack CLK3, but the contact region of thedicing blade DB and the semiconductor wafer may serve as the startingpoint. Namely, it is conceived that the crack CLK3 that occurs with thecontact region of the dicing blade DB and the semiconductor wafer beingas the starting point may be caused by a strong stress (force) in manycases. In this case, the crack CLK3 becomes large, and only with theconfiguration in which only the outer ring OUR1 is provided, apossibility increases that the large crack CLK3 breaks through the outerring OUR1, reaches even the seal ring SR located inside the outer ringOUR1, and destroys the seal ring SR.

Consequently, the outer ring OUR2 is provided outside the outer ringOUR1 in the present first embodiment. In this case, the crack CLK3 thatoccurs with the contact region of the dicing blade DB and thesemiconductor wafer being as the starting point first progresses fromthe scribe region SCR to the ring region RR, and reaches the outer ringOUR2. Although hopefully the crack CLK3 stops at this stage, it isassumed that the crack CLK3 breaks through the outer ring OUR2 dependingon a size of the crack CLK3. However, the outer ring OUR1 is providedinside the outer ring OUR2 in the present first embodiment. As a resultof this, according to the present first embodiment, it is conceived thateven though the crack CLK3 breaks through the outer ring OUR2, itreaches the outer ring OUR1 arranged inside the outer ring OUR2, andstops at the outer ring OUR1. Namely, in the present first embodiment,it is configured such that the crack CLK3 occurring by a comparativelystrong stress is stopped at either the outer ring OUR2, which is a firstbarrier, or the outer ring OUR1, which is a second barrier. That is, inthe present first embodiment, it is configured such that even the crackCLK3 occurring by the comparatively strong stress becomes difficult toreach even the seal ring SR formed inside the outer ring OUR1 by adouble barrier structure of the outer ring OUR2 and the outer ring OUR1.From this, the configuration in which the outer ring OUR2 is providedoutside the outer ring OUR1 is the useful configuration from a viewpointof preventing destruction of the seal ring SR due to the crack CLK3occurring by the comparatively strong stress.

From the above-mentioned reason, the outer ring OUR2 is provided outsidethe outer ring OUR1 in the present first embodiment. Additionally, thisouter ring OUR2 is arranged so as to overlap with the groove portion DITin plan view.

Hereinafter, this reason will be explained. For example, when the outerring OUR2 is arranged outside the groove portion DIT, it is necessary tosecure a space to arrange the outer ring OUR2 outside the groove portionDIT in the ring region RR. This means that a width of the ring region RRbecomes large, and a size of the chip region CR including the ringregion RR increases. Consequently, in the present first embodiment, theouter ring OUR2 is provided in the region that overlaps with the grooveportion DIT in plan view in order to reduce the size of the ring regionRR. In this case, increase of the size of the ring region RR byproviding the outer ring OUR2 can be suppressed.

Meanwhile, it is also conceived that the outer ring OUR2 is alsoarranged inside the groove portion DIT together with the outer ringOUR1. That is, it is conceived that the outer ring OUR1 and the outerring OUR2 are provided between the seal ring SR and the groove portionDIT. In this case, a distance between the outer ring OUR2, and aboundary line between the scribe region SCR and the ring region RRbecomes large. As a result of this, for example, as shown in FIG. 10,although progress of the crack CLK3 occurring with the contact region ofthe dicing blade DB and the semiconductor wafer being as the startingpoint stops at the outer ring OUR2, when the above-mentioned distancebetween the boundary line and the outer ring OUR2 becomes large, a partof the crack CLK3 remains in the semiconductor chip (in the ring regionRR) even after the chip region CR is separated into the semiconductorchips in the dicing step. Although the semiconductor chip is packaged ina subsequent step, it can also be conceived that the remaining crackCLK3 grows by a heat load or a stress applied in a packaging step, andeventually reaches even the seal ring SR to destroy the seal ring SR.Accordingly, the crack CLK3 that remains in the semiconductor chip isdesirably as small as possible. Thereby, it is useful that the outerring OUR2 is arranged as close as possible to the above-mentionedboundary line. The reason is that the smaller becomes theabove-mentioned distance between the boundary line and the outer ringOUR2, the smaller becomes a size of the crack CLK3 that remains in theseparated semiconductor chip (in the ring region RR), and the largeralso becomes a distance between the remaining crack CLK3 and the sealring SR. As a result of this, even if the heat load and a heat stress inthe subsequent packaging step are applied, a possibility of the growncrack CLK3 reaching the seal ring SR can be reduced. For this reason, inthe present first embodiment, the outer ring OUR2 is provided outsidethe outer ring OUR1, and this outer ring OUR2 is arranged so as tooverlap with the groove portion DIT in plan view.

From the discussion described above, in the present first embodiment,destruction of the seal ring SR due to the crack CLK2 can be effectivelyprevented by providing the outer ring OUR1 between the seal ring SR andthe groove portion DIT. Furthermore, in the present first embodiment,the outer ring OUR2 is provided outside the outer ring OUR1, and thisouter ring OUR2 is arranged so as to overlap with the groove portion DITin plan view. As a result of this, according to the present firstembodiment, a possibility can be increased that the crack CLK3 occurringby the comparatively strong stress stops at either the outer ring OUR2,which is the first barrier, or the outer ring OUR1, which is the secondbarrier. From this, according to the present first embodiment,destruction of the seal ring SR due to the crack CLK3 occurring by thecomparatively strong stress can also be prevented. As a result of this,in the present first embodiment, entering of moisture to the circuitregion LR due to destruction of the seal ring SR by the crack CLK2 andthe crack CLK3 can be reliably prevented, and thereby reliability of thesemiconductor wafer and the semiconductor chip (semiconductor device)obtained by dicing the semiconductor wafer can be improved.

Furthermore, according to the present first embodiment, the size of thechip region CR including the ring region RR can be reduced whilepreventing destruction of the seal ring SR due to the cracks CLK2 andCLK3. For example, in a case of a configuration in which the outer ringsOUR1 and OUR2 are not provided, there is a need to increase the distanceL1 shown in FIG. 10 in order to prevent destruction of the seal ring SRdue to the crack CLK2 that progresses to the seal ring SR side with thebottom of the groove portion DIT being as the starting point. This meansthat the size of the ring region RR becomes large, and since the ringregion RR constitutes a part of the chip region CR, eventually, the sizeof the chip region CR becomes large. As a result of this, the number ofthe semiconductor chips obtained from a single semiconductor waferdecreases, and thereby there is concern over the rise of manufacturingcost of the semiconductor device.

In contrast with this, in the present first embodiment, as shown in FIG.10, the outer ring OUR1 is provided between the seal ring SR and thegroove portion DIT, and the outer ring OUR2 is provided outside theouter ring OUR1 so as to planarly overlap with the groove portion DIT.These outer rings OUR1 and OUR2 have a function to stop the progress ofthe cracks CLK2 and CLK3, and to prevent destruction of the seal ring SRby the cracks CLK2 and CLK3 reaching even the seal ring SR. Namely,although it is desirable to largely secure the distance L1 between theseal ring SR and the groove portion DIT from a viewpoint of effectivelypreventing destruction of the seal ring SR, the outer rings OUR1 andOUR2 are provided in the present first embodiment, and thus destructionof the seal ring SR due to the cracks CLK2 and CLK3 can be fullyprevented even if the distance L1 shown in FIG. 10 is reduced.

That is, when a probability of the seal ring SR being destroyed is madethe same in the present first embodiment and the related art, theconfiguration in which the outer rings OUR1 and OUR2 are provided isemployed in the semiconductor wafer (or the semiconductor device) in thepresent first embodiment, and thus the above-mentioned distance L1 canbe reduced in the present first embodiment as compared with the relatedart. This means that the size of the ring region RR can be reduced whiledestruction of the seal ring SR due to the cracks CLK2 and CLK3 iseffectively prevented, and that eventually, the size of the chip regionCR can be reduced. As a result of this, according to the present firstembodiment, destruction of the seal ring SR due to the cracks CLK2 andCLK3 is prevented, and the number of chip regions CR that can be formedat a single semiconductor wafer can be increased. Namely, according tothe technical idea in the present first embodiment, it is possible toobtain a prominent effect that can reduce the manufacturing cost of thesemiconductor device while improving reliability of the semiconductorwafer and the semiconductor device.

When viewed from an opposite side, in the present first embodiment, whenthe distance L1 between the seal ring SR and the groove portion DIT ismaintained to be substantially a same length as the related art, theprobability of the seal ring SR being destroyed due to the cracks CLK2and CLK3 can be significantly reduced by means of a synergetic effect ofan effect that the distance L1 becomes large, and a barrier effect bythe outer rings OUR1 and OUR2.

From the discussion described above, according to the technical idea inthe present first embodiment, from a viewpoint of giving priority to aviewpoint that reduces a destruction probability of the seal ring SR,and reduces the manufacturing cost of the semiconductor device, theconfiguration can be employed in which the distance L1 between the sealring SR and the groove portion DIT is made smaller than the related art.Meanwhile, from a viewpoint of significantly reducing the destructionprobability of the seal ring SR due to the cracks CLK2 and CLK3, andgiving priority to further improvement in reliability of thesemiconductor device, while the outer rings OUR1 and OUR2 are provided,a configuration can be employed in which the distance L1 between theseal ring SR and the groove portion DIT is set to be substantially thesame as the related art. As described above, in the technical idea inthe present first embodiment, it is possible to obtain a prominenteffect that can also achieve the improvement of a degree of freedom ofdesign according to an object.

It is to be noted that in the present first embodiment, the seal ringSR, and the outer rings OUR1 and OUR2 are common in terms of allincluding a laminated structure that functions as a protection barrier.However, the seal ring SR, and the outer rings OUR1 and OUR2 originallydiffer in functions.

Namely, the seal ring SR has a function as the protection barrier thatprevents moisture from entering the circuit region LR that exists insidethe ring region RR. Accordingly, from a viewpoint of effectivelypreventing the entering of the moisture, it is necessary to prevent thedestruction of the seal ring SR by the cracks CLK2 and CLK3. That is,the seal ring SR is a component provided on a premise of not beingdestroyed. The reason is that when the seal ring SR is destroyed, itbecomes impossible to prevent the entering of the moisture from the ringregion RR to the circuit region LR, and thereby a harmful influence isexerted on the operational reliability of the integrated circuit formedin the circuit region LR, which eventually causes the decrease of thereliability of the semiconductor device.

In contrast with this, the outer rings OUR1 and OUR2 in the presentfirst embodiment have functions to stop the progress of the cracks CLK2and CLK3. Accordingly, as for the outer rings OUR1 and OUR2 in thepresent first embodiment, destruction of the outer rings OUR1 and OUR2themselves is not cared about as long as the progress of the cracks CLK2and CLK3 can be stopped. The reason is that as long as progress of thecracks CLK2 and CLK3 is stopped at the outer rings OUR1 and OUR2, thecracks CLK2 and CLK3 do not reach even the seal ring SR arranged insidethe outer ring OUR1, and destruction of the seal ring SR is prevented.

From this, the outer rings OUR1 and OUR2 in the present first embodimentdiffer from the seal ring SR on the premise of not being destroyed in apoint of having the components whose destruction is not cared about. Asdescribed above, while the seal ring SR, and the outer rings OUR1 andOUR2 have the configurations including the same laminated structure,there are features specific to the outer rings OUR1 and OUR2 from theabove-mentioned difference in the function. Hereinafter, the featurepoints will be explained.

A second feature point in the present first embodiment is the pointwhere a height of a top surface of the outer ring OUR1 is configuredhigher than a height of a top surface of the outer ring OUR2.Specifically, as shown in FIG. 10, for example, the outer ring OUR1includes a laminated structure including the first-layer metal patternMP2 to the sixth-layer metal pattern MP2 that overlap with one anotherin plan view, and the plugs that connect the metal patterns MP2 adjacentto each other in the lamination direction. Meanwhile, the outer ringOUR2 includes a laminated structure including the first-layer metalpattern MP3 to the fifth-layer metal pattern MP3 that overlap with oneanother in plan view, and the plugs that connect the metal patterns MP3adjacent to each other in the lamination direction. Accordingly, sincethe top surface of the outer ring OUR1 is a top surface of thesixth-layer metal pattern MP2, and the top surface of the outer ringOUR2 is a top surface of the fifth-layer metal pattern MP3, the heightof the outer ring OUR1 is higher than that of the outer ring OUR2.

Here, there will be explained a reason for making high the height of thetop surface of the outer ring OUR1. For example, in FIG. 10, the grooveportion DIT is formed in the surface protection film PAS, and the crackCLK2 occurs with the bottom of the groove portion DIT being as thestarting point. At this time, when the height of the top surface of theouter ring OUR1 is configured to be low, the crack CLK2 passes throughabove the outer ring OUR1, and a probability of the crack CLK2 reachingeven the seal ring SR increases. Namely, when the height of the topsurface of the outer ring OUR1 is low, a gap between the groove portionDIT and the top surface of the outer ring OUR1 is large, and the crackCLK2 is easy to pass through the gap. In other words, when the height ofthe top surface of the outer ring OUR1 is low, the crack CLK2 progressesto the seal ring SR side with the bottom of the groove portion DIT beingas the starting point. That is, when the height of the top surface ofthe outer ring; OUR1 is high, prevention of the progress to the sealring SR side of the crack CLK2 having occurred at the bottom of thegroove portion DIT becomes less effective.

Consequently, the height of the top surface of the outer ring OUR1 ismade high in the present first embodiment. Namely, the progress to theseal ring SR side of the crack CLK2 having occurred at the bottom of thegroove portion DIT can be effectively prevented by setting the topsurface of the outer ring OUR1 to be the top surface of the sixth-layermetal pattern MP2.

Note that it is conceived here that if the top surface of the outer ringOUR1 is made high, the outer ring OUR1 is configured so as to includenot only the sixth-layer metal pattern MP2 but also a metal pattern in asame layer as the metal pattern AMP. However, in the present firstembodiment, the outer ring OUR1 is not configured so as to include ametal pattern in a same layer as the metal pattern AMP formed in a toplayer of the seal ring SR.

This is based on a reason shown below. Namely, for example, thesecond-layer metal pattern MP2 to the sixth-layer metal pattern MP2include a fine copper pattern formed by the damascene method. Meanwhile,the metal pattern AMP formed in the top layer of the seal ring SR isformed by patterning an aluminum film. Additionally, in the same layeras the metal pattern AMP formed in the top layer of the seal ring SR,formed are a pad PD and the like that are formed in the circuit regionLR, and a wiring formed with a relatively large-sized coarse pattern,such as a power supply wiring. Accordingly, patterning of the aluminumfilm formed in the top layer of the seal ring SR is carried out with anaccuracy more moderate than the fine copper pattern formed in a lowerlayer by the damascene method. That is, a size of the metal pattern AMPformed in the top layer of the seal ring SR is much larger than that ofthe copper pattern formed in the lower layer.

From this, for example, when the outer ring OUR1 is configured so as toalso include the metal pattern in the same layer as the metal patternAMP, a width of the metal pattern of the top layer of the outer ringOUR1 is also much larger than widths of the first-layer metal patternMP2 to the sixth-layer metal pattern MP2.

This means that the width of the outer ring OUR1 becomes large, and thatthereby the distance L1 between the seal ring SR and the groove portionDIT shown in FIG. 10 becomes large. As a result of this, since the sizeof the ring region RR becomes large, and the ring region RR constitutesthe part of the chip region CR, eventually, the size of the chip regionCR becomes large. Thereby, the number of the semiconductor chipsobtained from a single semiconductor wafer decreases, and thereby thereis concern over the rise of manufacturing cost of the semiconductordevice. Accordingly, in the present first embodiment, from a viewpointof suppressing the increase of the size of the ring region RR, the outerring OUR1 is not configured so as to include the metal pattern in thesame layer as the metal pattern AMP formed in the top layer of the sealring SR.

From the discussion described above, in the present first embodiment,the configuration is employed in which the increase of the size of thering region RR is suppressed while the progress of the crack CLK2 havingoccurred at the bottom of the groove portion DIT to the seal ring SRside. Specifically, the outer ring OUR1 in the present first embodiment,for example, as shown in FIG. 10, includes the laminated structureincluding the first-layer metal pattern MP2 to the sixth-layer metalpattern MP2 that overlap with one another in plan view, and the plugsthat connect the metal patterns MP2 adjacent to each other in thelamination direction. In other words, the outer ring OUR1 in the presentfirst embodiment is configured so as not to directly come into contactwith the surface protection film PAS.

Subsequently, in the present first embodiment, the height of the topsurface of the outer ring OUR2 is made lower than the height of the topsurface of the outer ring OUR1. Hereinafter, this reason will beexplained. For example, the outer ring OUR2 is arranged so as to overlapwith the groove portion DIT in plan view (refer to FIG. 8). For thisreason, for example, in FIG. 10, it is conceived that when the height ofthe top surface of the outer ring OUR2 is made high, the top surface ofthe outer ring OUR2 is exposed from the bottom surface of the grooveportion DIT. In this case, the groove portion DIT and the outer ringOUR2 directly come into contact with each other.

Here, the groove portion DIT is provided with the purpose of allowingeasily to occur the crack CLK2 with the bottom of the groove portion DITbeing as the starting point in the dicing step.

However, when it is configured such that the height of the top surfaceof the outer ring OUR2 is high, and that the top surface of the outerring OUR2 is exposed from the bottom of the groove portion DIT, thebottom of the groove portion DIT cannot be made into the starting pointwhere the crack CLK2 occurs. That is, in order to make the bottom of thegroove portion DIT into the starting point of the crack CLK2, it isneeded that the bottom of the groove portion DIT and the top surface ofthe outer ring OUR2 are spaced apart from each other, and that theinterlayer insulating film is interposed in a region therebetween. Inother words, in order to make the groove portion DIT into the startingpoint of the crack CLK2, the semiconductor chip needs to be configuredsuch that the top surface of the outer ring OUR2 is not exposed from thebottom of the groove portion DIT.

Particularly, a distance between the bottom surface of the grooveportion DIT and the top surface of outer ring OUR2, for example, needsapproximately 100 nm. From this, the outer ring OUR2 in the presentfirst embodiment, for example, as shown in FIG. 10, includes a laminatedstructure including the first-layer metal pattern MP3 to the fifth-layermetal pattern MP3 that overlap with one another in plan view, and theplugs that connect the metal patterns MP3 adjacent to each other in thelamination direction. As a result of this, the height of the top surfaceof the outer ring OUR2 in the present first embodiment is lower than theheight of the top surface of the outer ring OUR1.

Next, a third feature point in the present first embodiment lies in apoint where, for example, as shown in FIG. 10, in the ring region RR,whereas the seal ring SR is configured to be connected to thesemiconductor substrate 1S, the outer rings OUR1 and OUR2 are arrangedabove the field insulating film STI formed at the semiconductorsubstrate 1S, and are arranged spaced apart from the field insulatingfilm STI.

Specifically, the plugs PLG2 are included in the seal ring SR, and theseal ring SR and the semiconductor substrate 1S are connected to eachother by these plugs PLG2. There will be explained a reason to connectthe seal ring SR and the semiconductor substrate 1S with the plugs PLG2.Namely, the seal ring SR has a function to prevent entering of moistureto the circuit region LR. Accordingly, it is needed that the seal ringSR is configured as a protection barrier without a gap that moistureenters. From this, the seal ring SR is configured to include the plugsPLG2, and to be connected to the semiconductor substrate 1S with theseplugs PLG2. From this, entering of the moisture from a surface of thesemiconductor substrate 1S is blocked by the plugs PLG2 constituting apart of the seal rings SR. From the discussion described above, the sealring SR in the present first embodiment is configured so as to beconnected to the semiconductor substrate 1S from a viewpoint ofeffectively preventing entering of the moisture to the circuit regionLR. At this time, for example, a reference potential may be supplied toa semiconductor region of the semiconductor substrate 1S connected tothe seal ring SR through the plugs PLG2, and in this case, the referencepotential is applied to the seal ring SR.

Meanwhile, as shown in FIG. 10, the outer rings OUR1 and OUR2 in thepresent first embodiment are arranged above the field insulating filmSTI formed on the semiconductor substrate 1S, and are arranged spacedapart from the field insulating film STI.

Hereinafter, this reason will be explained. Namely, the outer rings OUR1and OUR2 in the present first embodiment are mainly intended to preventprogress of the crack CLK2 or CLK3 occurring in the dicing step to theseal ring SR side. That is, unlike the seal ring SR, the outer ringsOUR1 and OUR2 in the present first embodiment are not mainly intended toprevent entering of the moisture to the circuit region LR. For thisreason, the outer rings OUR1 and OUR2 in the present first embodimentare arranged above the field insulating film STI formed on thesemiconductor substrate 1S, and are arranged spaced apart from the fieldinsulating film STI. However, particularly from the viewpoint ofsuppressing the progress of the crack CLK3 to the seal ring SR side, itseems that the outer rings OUR1 and OUR2 may also be, for example,better to be connected to the semiconductor substrate 1S through theplugs.

However, for example, when the outer rings OUR1 and OUR2 are alsoconfigured so as to be connected to the semiconductor substrate 1S, inthe ring region RR, the surface of the semiconductor substrate 1S formsa uniform flat surface from a lower layer of the seal ring SR to a lowerlayer of the outer rings OUR1 and OUR2. That is, the surface of thesemiconductor substrate 1S is flat in the ring region RR. In this case,since particularly moisture and foreign substances easily enter along aflat surface, from the viewpoint of effectively suppressing entering ofthe moisture to the circuit region LR, it should be avoided to configurealso the outer rings OUR1 and OUR2 to be connected to the semiconductorsubstrate 1S.

Consequently, in the present first embodiment, in order to avoid thatthe surface of the semiconductor substrate 1S is formed as the uniformflat surface in the ring region RR, while a configuration is employed inwhich the seal ring SR is connected to the semiconductor substrate 1S,the field insulating film STI is formed in the lower layer of the outerrings OUR1 and OUR2. In this case, since a height of a surface of thefield insulating film STI differs from a height of the surface of thesemiconductor substrate 1S, it can be suppressed that the uniform flatsurface is formed over the ring region RR. Namely, in the present firstembodiment, in the ring region RR, not the uniform flat surface but aconcavo-convex shaped surface is formed by the surface of thesemiconductor substrate 1S and the surface of the field insulating filmSTI that mutually differ in height. For this reason, according to thepresent first embodiment, entering of moisture and foreign substances tothe circuit region LR can be effectively suppressed. As described above,in the present first embodiment, the surface of the semiconductorsubstrate 1S and the surface of the field insulating film STI mixedlyexist in the ring region RR. Particularly, from a viewpoint ofeffectively preventing entering of the moisture and the foreignsubstances from the surface of the semiconductor substrate 1S, a regionin which the surface of the semiconductor substrate 1S is exposed likean island shape may be provided inside the field insulating film STI. Inthis case, since a further concavo-convex shape is formed on the surfaceof the field insulating film STI, entering of the moisture and theforeign substances to the circuit region LR can be effectivelyprevented. In the present first embodiment, the surface of the fieldinsulating film STI is formed higher than the surface of thesemiconductor substrate 1S, and thereby it is suppressed that the flatsurface is formed. However, the present invention is not limited to theabove height relation, and the surface of the field insulating film STIis formed lower than the surface of the semiconductor substrate 1S, andthereby it is also possible to suppress that the flat surface is formed

Here, in the present first embodiment, it is configured such that thefield insulating film STI is formed in the lower layer of the outerrings OUR1 and OUR2 from a viewpoint of not forming the uniform flatsurface. On this point, furthermore, on a premise of the above-mentionedconfiguration, particularly from a viewpoint of blocking a route for thecrack CLK3 to progress to the seal ring SR side, there is conceived aconfiguration in which the outer rings OUR1 and OUR2 are, for example,connected to the field insulating film STI with the plugs.

However, in a case of this configuration, for example, a contact hole isformed in an interlayer insulating film by using an etching technology,and a plug is formed by burying a conductive material in this contacthole.

At this time, for example, when the contact hole is formed in theinterlayer insulating film over the semiconductor substrate 1S by theetching technology like the seal ring SR, an etching selectivity can besecured since materials of an insulating film (for example, a siliconoxide film) constituting the interlayer insulating film, and of thesemiconductor substrate 1S (silicon) are different from each other. Forthis reason, when the contact holes are formed over the semiconductorsubstrate 1S, bottoms of the plurality of contact holes are aligned atthe surface of the semiconductor substrate 1S. As a result of this, theplugs PLG2 constituting the part of the seal rings SR can be accuratelyformed.

In contrast with this, for example, when a contact hole is formed in theinterlayer insulating film over the field insulating film STI by theetching technology like the outer rings OUR1 and OUR2, the etchingselectivity cannot be secured since materials of an insulating film (forexample, a silicon oxide film) constituting the interlayer insulatingfilm, and of a field insulating film (silicon oxide film) are a samekind. For this reason, when the contact holes are formed over the fieldinsulating film STI, the bottoms of the contact holes reach even aninside of the field insulating film STI, and scatter. As a result ofthis, the plugs that connect the outer rings OUR1 and OUR2, and thefield insulating film STI differ in size depending on products, anduniformity between the products is impaired. Accordingly, in the presentfirst embodiment, from a viewpoint of securing uniformity between theproducts, a configuration is not employed in which the outer rings OUR1and OUR2 are, for example, connected to the field insulating film STIwith the plugs.

From the discussion described above, in the present first embodiment, inthe ring region RR, whereas the seal ring SR is configured to beconnected to the semiconductor substrate 1S, the outer rings OUR1 andOUR2 are configured to be arranged above the field insulating film STIformed on the semiconductor substrate 1S, and to be arranged spacedapart from the field insulating film STI.

Subsequently, a fourth feature point in the present first embodiment is,for example, as shown in FIG. 8, the point where the width W2 of theouter ring OUR1 and the width W3 of the outer ring OUR2 are smaller thanthe width W1 of the seal ring SR. Thereby, even if the outer rings OUR1and OUR2 are provided in the chip region CR, increase of the size of thechip region CR can be suppressed to a minimum. For example, since theseal ring SR has the function as the protection barrier for preventingmoisture and foreign substances from entering the circuit region, it isnecessary to increase the width W1 of the seal ring SR to some extent.In contrast with this, the outer rings OUR1 and OUR2 may just stop theprogress of the crack to the seal ring SR side, and they are not mainlyintended to have the function to prevent entering of the moisture andthe foreign substances. Rather, increasing the width W2 of the outerring OUR1 and the width W3 of the outer ring OUR2 leads to the increaseof the chip region CR. As a result of this, in the present firstembodiment, the width W2 of the outer ring OUR1 and the width W3 of theouter ring OUR2 are made smaller than the width W1 of the seal ring SR.Specifically, for example, as shown in FIG. 10, the seal ring SR isconfigured to include the metal pattern AMP formed as the coarsepattern. In contrast with this, the outer ring OUR1 is configured not toinclude the metal pattern in the same layer as the metal pattern AMPconstituting the part of the seal ring SR, while to include thefirst-layer metal pattern MP2 to the sixth-layer metal pattern MP2 thatare formed as the fine pattern. Similarly, the outer ring OUR2 isconfigured not to include the metal pattern in the same layer as themetal pattern AMP constituting the part of the seal ring SR, while toinclude the first-layer metal pattern MP3 to the fifth-layer metalpattern MP3 that are formed as the fine pattern.

It is to be noted that the width W1 of the seal ring SR shown in FIG. 8is defined as a width of a widest metal pattern of the metal patternsconstituting the seal ring SR shown in FIG. 10. For example, since awidth of the metal pattern AMP formed at the top layer is the largest inthe seal ring SR shown in FIG. 10, the width W1 of the seal ring SRshown in FIG. 8 means a width of the metal pattern AMP shown in FIG. 10.

Meanwhile, the width W2 of the outer ring OUR1 shown in FIG. 8 isdefined as a width of a widest metal pattern of the metal patternsconstituting the outer ring OUR1 shown in FIG. 10. For example, sincewidths of the first-layer to sixth-layer metal patterns MP2 are the sameas one another in the outer ring OUR1 shown in FIG. 10, the width W2 ofthe outer ring OUR1 shown in FIG. 8 means the width of the metal patternMP2 constituting any of the first layer to the sixth layer shown in FIG.10.

Similarly, the width W3 of the outer ring OUR2 shown in FIG. 8 isdefined as a width of a widest metal pattern of the metal patternsconstituting the outer ring OUR2 shown in FIG. 10. For example, sincewidths of the first-layer to fifth-layer metal patterns MP3 are the sameas one another in the outer ring OUR2 shown in FIG. 10, the width W3 ofthe outer ring OUR2 shown in FIG. 8 means the width of the metal patternMP3 constituting any of the first layer to the fifth layer shown in FIG.10.

Next, a fifth feature point in the present first embodiment is, forexample, as shown in FIG. 8, the point where the distance X1 between theseal ring SR and the outer ring OUR1 is larger than the distance X2between the outer ring OUR1 and the outer ring OUR2. In other words, thefifth feature point in the present first embodiment can be said to bethe point where the distance X2 between the outer ring OUR1 and theouter ring OUR2 is smaller than the distance X1 between the seal ring SRand the outer ring OUR1. Furthermore, since the outer ring OUR2 overlapswith the groove portion DIT in plan view, it can be also said that inthe above-mentioned fifth feature point, the distance X1 between theseal ring SR and the outer ring OUR1 is larger than a distance betweenthe outer ring OUR1 and the groove portion DIT. In addition, as shown inFIG. 8, in the present first embodiment, the distance X1 between theseal ring SR and the outer ring OUR1 is larger than a distance betweenthe outer ring OUR1 and the outer peripheral line of the chip region CR.

This is a result of taking into consideration that since the seal ringSR needs to more reliably prevent entering of the moisture and theforeign substances to the circuit region LR, and to prevent destructiondue to the crack, it is desirably arranged in a region away from theouter peripheral line of the chip region CR as far as possible and nearthe circuit region LR. Furthermore, this is the result of taking intoconsideration of necessity of stopping the progress of the crack in anearly stage where the crack has occurred since the outer ring OUR1 hasthe function to prevent the progress of the crack to the seal ring SRside. From the discussion described above, in the present firstembodiment, the seal ring SR, the outer ring OUR1, the outer ring OUR2,and the groove portion DIT are arranged so that the above-mentionedrelation of the fifth feature point is established. Although the aboverelation has been explained in the region other than the corner CNR ofthe chip region CR, a relation in the corner CNR of the chip region CRwill be explained hereinafter.

In FIG. 8, also in the corner CNR, the distance Y1 between the seal ringSR and the outer ring OUR1 is larger than the distance Y2 between theouter rings OUR1 and OUR2. However, as shown in FIG. 8, a first spacebetween the seal ring SR and the outer ring OUR1 in the corner CNR ismuch larger than a second space between the seal ring SR and the outerring OUR1 other than the corner CNR.

This takes into consideration that a crack easily occurs at the cornerCNR. Namely, the crack easily occurs at the corner CNR of the chipregion CR compared with the outer peripheral region other than thecorner CNR. Particularly, the crack easily occurs that goes to theinside of the chip region CR from the corner CNR. In this case, forexample, when the distance Y1 between the corner CNR and the seal ringSR is small, the crack having occurred at the corner CNR easily reachesthe seal ring SR. As a result of this, the seal ring SR is destroyed bythe crack, and the seal ring SR does not fulfill the function as themoisture protection barrier. Thereby, moisture also enters the circuitregion, which is the inner region of the seal ring SR, which exerts theharmful influence on operational reliability of the integrated circuitformed in the circuit region.

From this, it is configured such that the seal ring SR has the inclinedpattern in the corner CNR of the chip region CR in the present firstembodiment. In this case, since the distance Y1 between the corner CNRand the seal ring SR is large, a crack can be suppressed from reachingeven the seal ring SR even though the crack occurs at the corner CNR andprogresses in the inner direction of the chip region CR. As a result ofthis, even if the crack occurs at the corner CNR in which the crackeasily occurs, the potential of the seal ring SR being destroyed by thecrack can be reduced. Namely, since the function of the seal ring SR asthe moisture protection barrier can be maintained even if the crackoccurs at the corner CNR, moisture can be prevented from entering eventhe circuit region LR, which is the inner region of the seal ring SR.From this, the operational reliability of the integrated circuit formedin the circuit region LR can be improved.

Meanwhile, as shown in FIG. 8, in the corner CNR, unlike the seal ringSR, the outer rings OUR1 and OUR2 are arranged even near the corner CNR.This results from a fact that the outer rings OUR1 and OUR2 have thefunction to stop the progress of the crack, and that there is no problemif the crack stops even though it is destroyed. Namely, in order toearly stop the crack having occurred at the corner CNR, also in thecorner CNR, the outer rings OUR1 and OUR2 are arranged even near thecorner CNR. Thereby, according to the present first embodiment, sincethe progress of the crack can be stopped early at the outer rings OUR1and OUR2 also in the corner CNR, destruction of the seal ring SR due tothe crack can be prevented. As a result of this, according to thepresent first embodiment, reliability of the semiconductor wafer and thesemiconductor chip (semiconductor device) obtained by dicing thesemiconductor wafer can be improved.

It is to be noted that in the present first embodiment, as shown in FIG.8, the distance X1 between the seal ring SR and the outer ring OUR1 isdefined as the distance between the outer peripheral line of the sealring SR and the inner peripheral line of the outer ring OUR1. Similarly,the distance X2 between the outer ring OUR1 and the outer ring OUR2 isdefined as the distance between the outer peripheral line of the outerring OUR1 and the inner peripheral line of the outer ring OUR2.Furthermore, although not shown in FIG. 8, a distance between the outerring OUR1 and the groove portion DIT is defined as the distance betweenthe outer peripheral line of the outer ring OUR1 and the innerperipheral line of the groove portion DIT.

<Manufacturing method of semiconductor device in First Embodiment>Subsequently, a manufacturing method of a semiconductor device in thepresent first embodiment will be explained with reference to thedrawings. First, as shown in FIG. 11, for example, the semiconductorsubstrate 1S including silicon single crystals is prepared. Thesemiconductor substrate 1S is a substantially disk-shaped semiconductorwafer shown in FIG. 1, has the plurality of chip regions CR, and thechip regions CR are partitioned by the scribe region SCR. It is to benoted that as shown in FIG. 11, the chip region CR has the circuitregion LR and the ring region RR, and the scribe region SCR is formedoutside the ring region RR.

Next, as shown in FIG. 12, a groove DIT1 is formed in the semiconductorsubstrate 1S by using a photolithography technology and the etchingtechnology. Additionally, as shown in FIG. 13 for example, an insulatingfilm including a silicon oxide film is deposited over the semiconductorsubstrate 1S in which the groove DIT1 has been formed, after that, CMP(Chemical Mechanical Polishing) is used for the deposited insulatingfilm, and thereby an unnecessary insulating film is polished. As aresult of this, the field insulating film STI can be formed as shown inFIG. 13. At this time, the surface of the semiconductor substrate 1S islower than the surface of the field insulating film STI, and a step isformed between the semiconductor substrate 1S and the field insulatingfilm STI.

After that, a field effect transistor TR is formed in the circuit regionLR as shown in FIG. 14. Specifically, over the semiconductor substrate1S, for example, formed is a gate insulating film including a siliconoxide film and a high dielectric constant film whose dielectric constantis higher than the silicon oxide film, and over the gate insulatingfilm, for example, formed is a gate electrode including a polysiliconfilm. Additionally, conductivity type impurities are introduced in thesemiconductor substrate 1S matched to the gate electrode using an ionimplantation method, and thereby a source region and a drain region areformed. In a manner described above, the field effect transistor TR canbe formed in the circuit region LR.

Subsequently, as shown in FIG. 15, an interlayer insulating film IL1 isformed over the semiconductor substrate 1S over which the field effecttransistor TR has been formed. The interlayer insulating film IL1 isformed all over the main surface of the semiconductor substrate 1Sincluding the chip region CR and the scribe region SCR.

Next, as shown in FIG. 16, contact holes are formed in the circuitregion LR and the ring region RR by using the photolithographytechnology and the etching technology, for example, a conductivematerial including tungsten is buried, and thereby the plugs PLG1 andPLG2 are formed. For example, the plugs PLG1 formed in the circuitregion LR are connected to the source region and the drain region of thefield effect transistor TR, and the plugs PLG2 formed in the ring regionRR are connected to the semiconductor substrate 1S.

After that, as shown in FIG. 17, a conductor film is formed over theinterlayer insulating film IL1 in which the plugs PLG1 and PLG2 havebeen formed, and the conductor film is patterned by using thephotolithography technology and the etching technology. Thereby, thewirings WL1 connected to the plugs PLG1 are formed in the circuit regionLR. Similarly, the metal patterns MP1 connected to the plugs PLG2 areformed in the ring region RR, and the metal patterns MP2 and MP3 areformed above the field insulating film STI formed in the ring region RR.The wirings WL1 and the metal patterns MP1 to MP3 are formed in a samelayer.

Subsequently, as shown in FIG. 18, an interlayer insulating film IL2 isformed over the interlayer insulating film IL1 in which the wirings WL1and the metal patterns MP1 to MP3 have been formed. Additionally, asshown in FIG. 19, a groove DIT2 is formed in the interlayer insulatingfilm IL2 by using the photolithography technology and the etchingtechnology. The groove DIT2 is formed in the circuit region LR and thering region RR, and in the circuit region LR, the groove DIT2 is formedso that a part of a surface of the wiring WL1 is exposed. Similarly,also in the ring region RR, the grooves DIT2 are formed so that parts ofthe surfaces of the metal patterns MP1 to MP3 are exposed.

Next, as shown in FIG. 20, for example, a copper film is formed over theinterlayer insulating film IL2 in which the grooves DIT2 have beenformed, and the copper film is buried inside the grooves DIT2. Afterthat, the unnecessary copper film formed over a surface of theinterlayer insulating film IL2 is removed by a CMP method. Thereby, thesecond-layer wiring WL1 connected to the first-layer wiring WL1 can beformed in the circuit region LR. Similarly, in the ring region RR, canbe formed the second-layer metal patterns MP1 connected to thefirst-layer metal patterns MP1, the second-layer metal pattern MP2connected to the first-layer metal pattern MP2, and the second-layermetal pattern MP3 connected to the first-layer metal pattern MP3.

After that, as shown in FIG. 21, the first-layer wiring WL1 to thesixth-layer wiring WL1 are formed in the interlayer insulating film ILin the circuit region LR by repeating similar steps. Meanwhile, thefirst-layer metal patterns MP1 to the sixth-layer metal patterns MP1 areformed in the ring region RR. Furthermore, in the ring region RR, thefirst-layer metal pattern MP2 to the sixth-layer metal pattern MP2 areformed, and the outer ring OUR1 including the first-layer to sixth-layermetal patterns MP2 is formed. Similarly, in the ring region RR, thefirst-layer metal pattern MP3 to the sixth-layer metal pattern MP3 areformed, and the outer ring OUR2 including the first-layer to fifth-layermetal patterns MP3 is formed.

Additionally, as shown in FIG. 22, after an interlayer insulating filmIL7 is formed, by using the photolithography technology and the etchingtechnology, an opening OP1 is formed in the interlayer insulating filmIL7 formed in the circuit region LR, and an opening OP2 is formed in theinterlayer insulating film IL7 formed in the ring region RR. The openingOP1 is formed so that a part of a surface of the sixth-layer wiring WL1is exposed, and the opening OP2 is formed so that parts of surfaces ofthe sixth-layer metal patterns MP1 are exposed.

Subsequently, as shown in FIG. 23, for example, a conductor filmincluding an aluminum film AF is formed over the interlayer insulatingfilm IL7 in which the openings OP1 and OP2 have been formed. After that,as shown in FIG. 24, the aluminum film AF is patterned by using thephotolithography technology and the etching technology. Thereby, the padPD connected to the sixth-later wiring WL1 is formed in the circuitregion LR, and the metal pattern AMP connected to the sixth-layer metalpattern MP1 is formed in the ring region RR. As a result of this, in thering region RR, formed is the seal ring SR including the plugs PLG2, thefirst-layer to sixth-layer metal patterns MP1, and the metal pattern AMPformed in an upper layer of the sixth-layer metal pattern MP1.

After that, as shown in FIG. 25, the surface protection film(passivation film) PAS is formed over the interlayer insulating film ILin which the pad PD and the metal pattern AMP have been formed.Additionally, as shown in FIG. 9, the surface protection film PAS isprocessed using the photolithography technology and the etchingtechnology, and thereby a part of a surface of the pad PD is exposed inthe circuit region LR, and the groove portion DIT that penetrates thesurface protection film PAS is formed in the ring region RR. The grooveportion DIT is formed at a position that overlaps with the outer ringOUR2 in plan view, the position being outside the outer ring OUR1.According to such a manner as described above, the semiconductor waferin the present first embodiment can be manufactured.

Next, the scribe region SCR formed at the semiconductor wafer is cutoff, for example, by a rotating dicing blade, and thereby the pluralityof chip regions CR is separated to produce the plurality ofsemiconductor chips. At this time, in the present first embodiment, inthe scribe region SCR located outside the ring region RR being cut offby the dicing blade, a crack can be prevented from reaching even theseal ring SR that exists in the ring region RR. That is, in the presentfirst embodiment, since the outer rings OUR1 and OUR2 are providedoutside the seal ring SR, the crack reaches the outer ring OUR1 or theouter ring OUR2 before reaching the seal ring SR, and stops there. As aresult of this, according to the present first embodiment, the crackoccurring in the dicing step can be prevented from reaching even theseal ring SR that exists in the ring region RR. As a result of this,according to the present first embodiment, even if the crack occurs dueto the dicing step, destruction of the seal ring SR due to the crack canbe prevented. Thereby, according to the present first embodiment, sinceentering of moisture and foreign substances to the circuit region LR canbe suppressed by the seal ring SR, reliability of the semiconductor chipcan be improved. After that, the semiconductor device in the presentfirst embodiment can be manufactured through the packaging step.

Second Embodiment

In the present second embodiment, there will be explained an examplewhere the width of the outer ring OUR2 is larger than the width of thegroove portion DIT, and an outer peripheral line of the outer ring OUR2is located more inside than an outer peripheral side surface of thegroove portion DIT.

FIG. 26 is a cross-sectional view showing a configuration of asemiconductor wafer in the present second embodiment. In FIG. 26, sincethe semiconductor wafer in the present second embodiment has asubstantially similar configuration to the semiconductor wafer in thefirst embodiment shown in FIG. 9, differences will be mainly explained.

A feature of the present second embodiment lies in the point that thewidth L2 of the outer ring OUR2 is larger than the width L3 of thegroove portion DIT as shown in FIG. 26. At this time, the outer ringOUR2 is configured to include the first-layer to fifth-layer metalpatterns MP3, and the width of the metal pattern MP3 corresponds to thewidth L2 of the outer ring OUR2. Additionally, as shown in FIG. 26, inthe present second embodiment, on a premise that the width L2 of theouter ring OUR2 is larger than the width L3 of the groove portion DIT,the outer peripheral line of the outer ring OUR2 is arranged more insidethan the outer peripheral side surface of the groove portion DIT.

Thereby, for example, in the dicing step, a possibility can be madehigher that a crack that progresses to the seal ring SR side with thebottom of the groove portion DIT being as the starting point bumpsagainst the outer ring OUR2 with a large width L2, and then stops.Namely, although the crack that progresses to the seal ring SR side withthe bottom of the groove portion DIT being as the starting point has ahigh probability to mainly stop at the outer ring OUR1 arranged insidethe groove portion DIT, furthermore, in the present second embodiment,the outer ring OUR2 that overlaps with the groove portion DIT protrudesinside the groove portion DIT in plan view. For this reason, the crackthat progresses to the seal ring SR side with the bottom of the grooveportion DIT being as the starting point can be stopped also by the outerring OUR2. That is, with the configuration of the present secondembodiment, since the probability is high to stop the crack thatprogresses to the seal ring SR side with the bottom of the grooveportion DIT being as the starting point not only by the outer ring OUR1but by the outer ring OUR2, destruction of the seal ring SR due to thecrack can be effectively prevented.

Furthermore, in the present second embodiment, since the widths of thefirst-layer to fifth-layer metal patterns MP3 constituting the outerring OUR2 are set to be large, for example, it also becomes possible toconnect the metal patterns MP3 arranged in layers adjacent to each otherin the lamination direction with the plurality of plugs. This means thatimproved is a strength of a laminated structure including the plugs thatconnect the first-layer to fifth-layer metal patterns MP3 and the metalpatterns MP3 adjacent to each other in the lamination direction. In thiscase, for example, also with respect to a crack that occurs with thecontact region of the dicing blade and the semiconductor wafer being asthe starting point since a force (stress) applied to the semiconductorwafer in the dicing step is too strong, progress of the crack can bestopped by the outer ring OUR2 whose strength is enhanced. That is,according to the present second embodiment, since a reaching probabilityof the crack to the seal ring SR can be significantly reduced by a pointwhere a structural strength of the outer ring OUR2 has been improved,and a synergetic effect of a double protection barrier structure of theouter ring OUR2 and the outer ring OUR1, destruction of the seal ring SRdue to the crack can be effectively prevented.

Third Embodiment

In the present third embodiment, there will be explained an examplewhere the outer ring OUR1 is configured to include not only the plugsthat connect the first-layer to sixth-layer metal patterns MP2 and themetal patterns MP2 adjacent to each other in the lamination direction,but metal patterns in an upper layer of the sixth-layer metal patternsMP2.

FIG. 27 is a cross-sectional view showing a configuration of asemiconductor wafer in the present third embodiment. In FIG. 27, sincethe semiconductor wafer in the present third embodiment has asubstantially similar configuration to the semiconductor wafer in thefirst embodiment shown in FIG. 9, differences will be mainly explained.

In FIG. 27, a feature of the present third embodiment lies in the pointthat the outer ring OUR1 is configured to include also a metal patternAMP2. That is, the outer ring OUR1 is configured to include the metalpattern AMP2 formed in a same layer as the pad PD formed in the circuitregion LR and the metal pattern AMP constituting the top layer of theseal ring SR.

In this case, the outer ring OUR1 is configured to directly come intocontact with the surface protection film PAS by the metal pattern AMP2.Additionally, in the present third embodiment, since the top surface ofthe outer ring OUR1 serves as a top surface of the top-layer metalpattern AMP2, the top surface of the outer ring OUR1 is higher than thebottom surface of the groove portion DIT. As a result of this, accordingto the present third embodiment, a probability can be increased that thecrack that progresses to the seal ring SR side with the bottom of thegroove portion DIT being as the starting point is blocked by the outerring OUR1 to stop.

Fourth Embodiment

In the present fourth embodiment, there will be explained an examplewhere the groove portion DIT penetrates the surface protection film PASto be formed halfway through the interlayer insulating film.

FIG. 28 is a cross-sectional view showing a configuration of asemiconductor wafer in the present fourth embodiment. In FIG. 28, sincethe semiconductor wafer in the present fourth embodiment has asubstantially similar configuration to the semiconductor wafer in thefirst embodiment shown in FIG. 9, differences will be mainly explained.

In FIG. 28, a feature of the present fourth embodiment lies in the pointthat the groove portion DIT penetrates the surface protection film PASto be formed halfway through the interlayer insulating film. As a resultof this, in the present fourth embodiment, the top surface of the outerring OUR1 is higher than the bottom surface of the groove portion DIT.Thereby, according to the present fourth embodiment, the probability canbe increased that the crack that progresses to the seal ring SR sidewith the bottom of the groove portion DIT being as the starting point isblocked by the outer ring OUR1 to stop.

Here, the configuration of the present fourth embodiment and theconfiguration of the third embodiment are common in a point where thetop surface of the outer ring OUR1 is made higher than the bottomsurface of the groove portion DIT, but when the viewpoint of suppressingthe increase of the chip region CR is taken into consideration, theconfiguration of the present fourth embodiment has superiority to theconfiguration of the third embodiment.

Namely, in the above-described third embodiment, the metal pattern AMP2is formed in the top layer of the outer ring OUR1, and thereby the topsurface of the outer ring OUR1 is made higher than the bottom surface ofthe groove portion DIT. The metal pattern AMP2 is the pattern with alarge size formed of an aluminum film in a same layer as the pad PD, andwhen the outer ring OUR1 is configured to include the metal pattern AMP2with the large size, inevitably, the size of the ring region RR becomeslarge.

In contrast with this, in the present fourth embodiment, while the toplayer of the outer ring OUR1 includes the fine sixth-layer metal patternMP2, the groove portion DIT is deeply formed halfway through theinterlayer insulating film, and thereby the top surface of the outerring OUR1 is made higher than the bottom surface of the groove portionDIT. As described above, in the present fourth embodiment, as comparedwith the above-described third embodiment, the top surface of the outerring OUR1 can be made higher than the bottom surface of the grooveportion DIT, while the width of the outer ring OUR1 is reduced. As aresult of this, according to the present fourth embodiment, whileincrease of the size of the chip region CR including the ring region RRis suppressed, the probability can be increased that the crack thatprogresses to the seal ring SR side with the bottom of the grooveportion DIT being as the starting point is stopped by the outer ringOUR1.

Fifth Embodiment

In the present fifth embodiment, there will be explained an examplewhere a depth of the groove portion DIT is made much deeper than in thefourth embodiment.

FIG. 29 is a cross-sectional view showing a configuration of asemiconductor wafer in the present fifth embodiment. In FIG. 29, sincethe semiconductor wafer in the present fifth embodiment has asubstantially similar configuration to the semiconductor wafer in thefirst embodiment shown in FIG. 9, differences will be mainly explained.

In FIG. 29, a feature of the present fifth embodiment lies in the pointthat the depth of the groove portion DIT is made deeper than in thefourth embodiment. Specifically, in the above-described fourthembodiment shown in FIG. 28, the bottom of the groove portion DIT islocated above the outer ring OUR2 including the first-layer tofifth-layer metal patterns MP3. In contrast with this, in the presentfifth embodiment shown in FIG. 29, the bottom of the groove portion DITis located above the outer ring OUR2 including the first-layer tofourth-layer metal patterns MP3. Accordingly, the bottom of the grooveportion DIT in the present fifth embodiment is formed deeper byapproximately one layer as compared with the bottom of the grooveportion DIT in the fourth embodiment.

Also in the present fifth embodiment configured as described above, thetop surface of the outer ring OUR1 is higher than the bottom surface ofthe groove portion DIT similarly to the above-described fourthembodiment. Thereby, also according to the present fifth embodiment, theprobability can be increased that the crack that progresses to the sealring SR side with the bottom of the groove portion DIT being as thestarting point is blocked by the outer ring OUR1 to stop.

Here, the present fifth embodiment has the configuration in which sincethe depth of the groove portion DIT is deeper as compared with thefourth embodiment, a crack easily occurs from the bottom of the grooveportion DIT. Namely, the crack occurs more easily from the bottom of thegroove portion DIT of the present fifth embodiment than in the bottom ofthe groove portion DIT of the fourth embodiment. On this point, althoughthe groove portion DIT is provided to intentionally make the crack occurfrom the bottom of the groove portion DIT, nonetheless, there is no needto increase an occurrence probability of the crack. That is, as long asthe crack does not occur, there is no possibility that the seal ring SRis destroyed by the crack, and thus there is no need to purposelyincrease the occurrence probability of the crack. Namely, the depth ofthe groove portion DIT may just be specified at a level where the grooveportion DIT is more easily broken than the other region, and there is noneed to purposely increase the occurrence probability of the crack byunnecessarily making deeper the depth of the groove portion DIT. Whenthe above is taken into consideration, the fourth embodiment can be saidto have superiority to present fifth embodiment from a viewpoint ofreducing the occurrence probability of the crack.

However, in the present fifth embodiment, although the crack with thebottom of the groove portion DIT being as the starting point easilyoccurs, a difference in height of the top surface of the outer ring OUR1and the bottom surface of the groove portion DIT is large, and thus theprobability can be increased that the crack that progresses to the sealring SR side with the bottom of the groove portion DIT being as thestarting point is blocked by the outer ring OUR1 to stop.

Sixth Embodiment

In the present sixth embodiment, there will be explained an examplewhere the outer rings OUR1 and OUR2 are connected to the fieldinsulating film STI.

FIG. 30 is a cross-sectional view showing a configuration of asemiconductor wafer in the present sixth embodiment. In FIG. 30, sincethe semiconductor wafer in the present sixth embodiment has asubstantially similar configuration to the semiconductor wafer in thefirst embodiment shown in FIG. 9, differences will be mainly explained.

In FIG. 30, a feature of the present sixth embodiment lies in the pointthat the outer ring OUR1 is connected to the field insulating film STIby a plug PLG3, and that the outer ring OUR2 is connected to the fieldinsulating film STI by a plug PLG4.

In this case, entering of moisture and foreign substances to the circuitregion LR can be effectively prevented by the outer rings OUR1 and OUR2.That is, although the outer rings OUR1 and OUR2 are formed mainly forthe purpose of stopping the progress of the crack, in the present sixthembodiment, furthermore, the outer rings OUR1 and OUR2 increase aneffect of preventing entering of the moisture or the foreign substances.Particularly, in the present sixth embodiment, entering of the moistureto the circuit region LR can be effectively prevented by a synergeticeffect of a point where the seal ring SR is provided, a point where astep is formed between the surface of the semiconductor substrate 1S towhich the seal ring SR has been connected and the surface of the fieldinsulating film STI, and a point where the outer rings OUR1 and OUR2 areconnected to the field insulating film STI.

However, as explained in the above-described first embodiment, when theouter rings OUR1 and OUR2, and the field insulating film STI areconnected by the plugs PLG3 and PLG4, sizes of the plugs PLG3 and PLG4differ depending on products, and uniformity among the products isimpaired. For this reason, the configuration of the present sixthembodiment is the particularly useful configuration when entering of themoisture and the foreign substances to the circuit region LR is reliablyprevented to give priority to the improvement in reliability of thesemiconductor device even though the uniformity among the products isimpaired to some extent.

It is to be noted that for example, there is a technology, for example,called SAC (Self Align Contact), in a manufacturing technology of asemiconductor device. In the technology called SAC, after the fieldeffect transistor TR is formed, a silicon nitride film is formed so asto cover the field effect transistor TR, and after that, a silicon oxidefilm that serves as the interlayer insulating film is formed over thesilicon nitride film. Accordingly, when the technology called SAC isused, in FIG. 30, a laminated film of a silicon nitride film and asilicon oxide film is formed also over the field insulating film STI inthe ring region RR. Accordingly, first, when the silicon oxide film,which is the interlayer insulating film, is etched to forma contacthole, the silicon nitride film that exists at a lower layer serves as anetching stopper. Subsequently, when the silicon nitride film is etched,the field insulating film STI that exists at the lower layer of thesilicon nitride film is formed of the silicon oxide film, and thus thefield insulating film STI serves as an etching stopper. From this, whenthe technology called SAC is used, the contact hole that penetrates theinterlayer insulating film and the silicon nitride film becomes hard toetch even to the field insulating film STI. This means that it ispossible to enhance uniformity of the sizes of the plug PLG3 thatconnects the outer ring OUR1 and the field insulating film STI, and ofthe plug PLG4 that connects the outer ring OUR2 and the field insulatingfilm STI. That is, when the technology called SAC is used, without theuniformity among the products being impaired, the outer ring OUR1 andthe field insulating film STI can be connected to each other by the plugPLG3, and the outer ring OUR2 and the field insulating film STI can beconnected to each other by the plug PLG4. As a result of this, an effectof preventing entering of the moisture and the foreign substances to thecircuit region LR can be improved while uniformity among the products isenhanced.

Seventh Embodiment

In the present seventh embodiment, there will be explained an examplewhere a dummy pattern or a corner reinforcing pattern is providedbetween the seal ring SR and the outer ring OUR1 in plan view.

FIG. 31 is a view showing a planar layout configuration near the cornerCNR of the chip region CR. As shown in FIG. 31, the seal ring SR isformed in the chip region CR having the corner CNR. This seal ring SR isarranged so as to extend along an outer peripheral line of the chipregion CR in a region other than the corner CNR, and is arranged so asto be spaced apart from the corner CNR at the corner CNR. Namely, theseal ring SR is, as shown in FIG. 31, arranged so that the distancebetween the corner CNR and the seal ring SR is larger than the distancebetween the outer peripheral line of the chip region CR in the regionother than the corner CNR and the seal ring SR.

Subsequently, in the present seventh embodiment, the groove portion(slit) DIT is arranged along the outer peripheral line of the chipregion CR. Specifically, as shown in FIG. 31, the groove portion DITextends along the outer peripheral line of the chip region CR includingthe corner CNR. At this time, the groove portion DIT is arranged outsidethe seal ring SR in plan view. That is, the groove portion DIT isarranged so as to be sandwiched between the outer peripheral line of thechip region CR and the seal ring SR in plan view.

Additionally, in the present seventh embodiment, in plan view, the outerring OUR1 is provided between the groove portion DIT and the seal ringSR, and the outer ring OUR1 also extends along the outer peripheral lineof the chip region CR. Furthermore, in the present seventh embodiment,the outer ring OUR2 is provided outside the outer ring OUR1, and theouter ring OUR2 also extends along the outer peripheral line of the chipregion CR. Particularly, the outer ring OUR2 is arranged so as tooverlap with the groove portion DIT in plan view.

Here, a feature of the present seventh embodiment lies in the point thatas shown in FIG. 31, a plurality of dummy patterns DMY2 is arranged in asecond space between the seal ring SR and the outer ring OUR1 whenplanarly viewed in a region other than the corner CNR. Furthermore, afeature of the present seventh embodiment lies in the point that nearthe corner CNR, a plurality of corner reinforcing patterns LSS isarranged in a first space between the seal ring SR and the outer ringOUR1 when planarly viewed. At this time, an area of the first space islarger than that of the second space as shown in FIG. 31. Additionally,the dummy patterns DMY2 arranged in the second space each have asubstantially square shape in plan view, and are arranged side by sidealong the outer peripheral line of the chip region CR. Meanwhile, thecorner reinforcing patterns LSS arranged in the first space constitutesa line segment structure having a line segment shape. The plurality ofline segment structures (eight in FIG. 31) arranged in the first spaceis formed side by side in an extending direction of a bisector, whilecrossing (bisecting) to the bisector of the corner CNR.

According to the present seventh embodiment configured as describedabove, the following effects can be obtained. Namely, a crack occursmore easily in the corner CNR than in regions of sides other than thecorner CNR, and there is a high risk that a crack that progresses in adirection from the corner CNR to the inside of the chip region CRparticularly exerts a harmful influence on the reliability of thesemiconductor device. For this reason, in the present seventhembodiment, in the region (first space) that goes to the inside of thechip region CR from the corner CNR, formed is the corner reinforcingpattern LSS whose area is larger than the dummy pattern DMY2, and thatincludes the line segment structures arranged side by side so as tocross the bisector of the corner CNR when planarly viewed. Particularly,in the present seventh embodiment, the corner reinforcing pattern LSSincluding the line segment structures is formed as large as possible,and thereby crack resistance in the corner CNR can be improved.Meanwhile, in order to improve the crack resistance in the region otherthan the corner CNR although not so much as the corner CNR, theplurality of dummy patterns DMY2 is arranged in the second space betweenthe seal ring SR and the outer ring OUR1. As a result of this, accordingto the present seventh embodiment, entering of the crack in an innerdirection can be suppressed all over the outer peripheral line of thechip region CR.

FIG. 32 is a cross-sectional view taken along a line A-A of FIG. 31. InFIG. 32, it can be seen that the dummy pattern DMY2 is formed betweenthe seal ring SR and the outer ring OUR1. The dummy pattern DMY2includes a first-layer metal pattern MP4 to a sixth-layer metal patternMP4. At this time, although the first-layer to sixth-layer metalpatterns MP4 includes patterns with a same width, they may includepatterns with different widths.

As shown in FIG. 32, for example, it is conceived that the crack thatprogresses to the seal ring SR side with the bottom of the grooveportion DIT being as the starting point stops at the outer ring OUR1.However, in the present seventh embodiment, furthermore, since the dummypattern DMY2 having a function to prevent the progress of the crack isformed between the seal ring SR and the outer ring OUR1, the crack canbe stopped by the dummy pattern DMY2 even if the progress of the crackdoes not stop at the outer ring OUR1. As a result of this, according tothe present seventh embodiment, destruction of the seal ring SR due tothe crack can be further prevented.

FIG. 33 is a cross-sectional view taken along a line B-B of FIG. 31. Asshown in FIG. 33, it can be seen that in a corner, eight cornerreinforcing patterns LSS are arranged side by side between the seal ringSR and the outer ring OUR1. Additionally, the individual cornerreinforcing pattern LSS includes a first layer to sixth-layer metalpatterns MP5, and plugs that connect the metal patterns MP5 in layersadjacent to each other in the lamination direction.

In the corner configured as described above, since eight cornerreinforcing patterns LSS are provided further inside, progress of acrack can be reliably stopped by these corner reinforcing patterns LSSeven though the crack is the one that cannot be stopped by either theouter ring OUR2, which is the first barrier, or the outer ring OUR1,which is the second barrier. As a result of this, destruction of theseal ring SR particularly due to a large crack that easily occurs in thecorner CNR can also be reliably prevented. Thereby, in the presentseventh embodiment, entering of moisture to the circuit region LR due todestruction of the seal ring SR by the crack can be reliably prevented,and thereby reliability of the semiconductor wafer and the semiconductorchip (semiconductor device) obtained by dicing the semiconductor wafercan be improved.

Eighth Embodiment

In the present eighth embodiment, there will be explained an examplewhere a plurality of dummy patterns DMY1 is arranged also outside thecorner reinforcing patterns LSS. Since a configuration of the presenteighth embodiment is substantially similar to the seventh embodiment,differences will be mainly explained.

FIG. 34 is a view showing a planar layout configuration near the cornerCNR of the chip region CR. In FIG. 34, a feature of the present eighthembodiment lies in the point that in the corner CNR, the plurality ofcorner reinforcing patterns LSS is arranged in the first space betweenthe seal ring SR and the outer ring OUR1, and the plurality of dummypatterns DMY1 is provided also between the corner reinforcing patternLSS and the outer ring OUR1.

According to the present eighth embodiment configured as describedabove, the following effects can be obtained. Namely, in theabove-described seventh embodiment, although the whole corner CNR can bereinforced, the corner reinforcing pattern LSS planarly has a largerarea than the dummy pattern DMY2. For this reason, there is alsoconceived a case where it is difficult to form the corner reinforcingpattern LSS even near the sides of the chip region CR also in the firstspace of the corner CNR. Consequently, in order to protect a vicinity ofthe sides of the chip region CR also in the first space of the cornerCNR, and in order to stop a crack at a position away from the seal ringSR as far as possible also in the corner CNR, the plurality of dummypatterns DMY2 is arranged outside the corner reinforcing pattern LSS inthe corner CNR. Thereby, according to the present eighth embodiment, thecorner reinforcing pattern LSS and the dummy pattern DMY1 are combinedwith each other in the corner CNR, and thereby the whole corner CNR canbe reinforced and the vicinity of the sides near the corner CNR can alsobe reinforced.

FIG. 35 is a cross-sectional view taken along a line A-A of FIG. 34. InFIG. 35, it can be seen that the dummy pattern DMY2 is formed betweenthe seal ring SR and the outer ring OUR1. The dummy pattern DMY2includes the first-layer metal pattern MP4 to the sixth-layer metalpattern MP4. At this time, although the first-layer to sixth-layer metalpatterns MP4 include patterns with a same width, they may includepatterns with different widths.

In addition, FIG. 36 is across-sectional view taken along a line B-B ofFIG. 34. As shown in FIG. 36, it can be seen that in the corner, sevencorner reinforcing patterns LSS are arranged side by side between theseal ring SR and the outer ring OUR1. Additionally, the individualcorner reinforcing pattern LSS includes the first layer to sixth-layermetal patterns MP5, and plugs that connect the metal patterns MP5 in thelayers adjacent to each other in the lamination direction. Additionally,it can be seen that the dummy pattern DMY1 is formed between the cornerreinforcing pattern LSS arranged outermost and the outer ring OUR1. Thedummy pattern DMY1 includes the first-layer metal pattern MP4 to thesixth-layer metal pattern MP4. At this time, although the first-layer tosixth-layer metal patterns MP4 include patterns with a same width, theymay include patterns with different widths.

In the present eighth embodiment, by a synergetic effect by providingthe outer rings OUR1 and OUR2, and by providing the corner reinforcingpattern LSS, and the dummy patterns DMY1 and DMY2, entering of moistureto the circuit region LR due to destruction of the seal ring SR by thecrack can be reliably prevented. As a result of this, according to thepresent eighth embodiment, reliability of the semiconductor wafer andthe semiconductor chip (semiconductor device) obtained by dicing thesemiconductor wafer can be improved.

Ninth Embodiment

In the present ninth embodiment, there will be explained an examplewhere while the outer ring OUR1 is provided, the outer ring OUR2 is notprovided.

FIG. 37 is a view showing a planar layout configuration near the cornerCNR of the chip region CR. As shown in FIG. 37, the seal ring SR isformed in the chip region CR having the corner CNR. The seal ring SR isarranged so as to extend along the outer peripheral line of the chipregion CR in a region other than the corner CNR, and is arranged so asto be spaced apart from the corner CNR at the corner CNR. Namely, theseal ring SR is, as shown in FIG. 37, arranged so that the distancebetween the corner CNR and the seal ring SR is larger than the distancebetween the outer peripheral line of the chip region CR in the regionother than the corner CNR and the seal ring SR.

Additionally, in the present ninth embodiment, the groove portion (slit)DIT is arranged along the outer peripheral line of the chip region CR.Specifically, as shown in FIG. 37, the groove portion DIT extends alongthe outer peripheral line of the chip region CR including the cornerCNR. At this time, the groove portion DIT is arranged outside the sealring SR in plan view. That is, the groove portion DIT is arranged so asto be sandwiched between the outer peripheral line of the chip region CRand the seal ring SR in plan view. Furthermore, in the present ninthembodiment, in plan view, the outer ring OUR1 is provided between thegroove portion DIT and the seal ring SR, and the outer ring OUR1 alsoextends along the outer peripheral line of the chip region CR.

FIG. 38 is a cross-sectional view taken along a line A-A of FIG. 37. Asshown in FIG. 38, in the ninth embodiment, although the outer ring OUR1is provided between the seal ring SR and the groove portion DIT in thering region RR, the outer ring OUR2 that planarly overlaps with thegroove portion DIT is not provided.

Also in such a configuration of the present ninth embodiment, forexample, in the scribe region SCR located outside the ring region RRbeing cut off by a dicing blade, a crack can be prevented from reachingeven the seal ring SR that exists in the ring region RR. That is, sincethe outer ring OUR1 is provided outside the seal ring SR even in thepresent ninth embodiment, the crack reaches the outer ring OUR1 beforereaching the seal ring SR, and stops there. As a result of this,according to the present ninth embodiment, the crack occurring in thedicing step can be prevented from reaching even the seal ring SR thatexists in the ring region RR.

Here, a main reason that the outer ring OUR1 is provided outside theseal ring SR and also inside the groove portion DIT is to prevent fromreaching even the seal ring SR a crack that progresses to the seal ringSR side with the bottom of the groove portion DIT being as the startingpoint. Furthermore, the outer ring OUR1 also has a function to preventthe progress of the crack to the seal ring SR side even if a crack witha contact region of a dicing blade and the semiconductor wafer being asthe starting point occurs. Accordingly, even when the outer ring OUR2 isnot provided outside the outer ring OUR1 as in the present ninthembodiment, destruction of the seal ring SR due to the crack with thebottom of the groove portion DIT being as the starting point, and thecrack with the contact region of the dicing blade and the semiconductorwafer can be prevented by the outer ring OUR1. As a result of this, alsoin the present ninth embodiment, reliability of the semiconductor waferand the semiconductor chip (semiconductor device) obtained by dicing thesemiconductor wafer can be improved.

Tenth Embodiment

In the present tenth embodiment, there will be explained a configurationin a case of carrying out the dicing step by laser dicing.

FIG. 39 is a view showing a planar layout configuration near the cornerCNR of the chip region CR. As shown in FIG. 39, the seal ring SR isformed in the chip region CR having the corner CNR. The seal ring SR isarranged so as to extend along the outer peripheral line of the chipregion CR in the region other than the corner CNR, and is arranged so asto be spaced apart from the corner CNR at the corner CNR. Namely, theseal ring SR is, as shown in FIG. 39, arranged so that the distancebetween the corner CNR and the seal ring SR is larger than the distancebetween the outer peripheral line of the chip region CR in the regionother than the corner CNR and the seal ring SR.

Additionally, in the present tenth embodiment, when planarly viewed, theouter ring OUR1 is provided between the outer peripheral line of thechip region CR and the seal ring SR, and the outer ring OUR1 extendsalong the outer peripheral line of the chip region CR. At this time, thewidth of the outer ring OUR1 is smaller than that of the seal ring SR.

FIG. 40 is a cross-sectional view taken along a line A-A of FIG. 39. Asshown in FIG. 40, in the present tenth embodiment, the outer ring OUR1is provided between the seal ring SR and an outer peripheral line of thering region RR. The outer ring OUR1 is, for example, arranged in aregion near the outer peripheral line of the ring region RR if possible.Specifically, a distance between the outer peripheral line of the ringregion RR and the outer ring OUR1 is smaller than a distance between theouter ring OUR1 and the seal ring SR.

Thereby, the following effects can be obtained. Namely, FIG. 40 showsthe dicing step in which the scribe region SCR is cut off by irradiatingthe scribe region SCR of the semiconductor wafer with the laser lightLAR. In FIG. 40, a technology called laser dicing is the technology inwhich the semiconductor wafer is irradiated with the laser light LAR andan irradiation region is heated, and thereby the irradiation region ofthe semiconductor wafer is burned to be cut off. In this case, since notonly the region irradiated with the laser light LAR but a peripheralregion of the irradiation region is heated, a film burns and disappearsalso in the peripheral region. At this time, flammability of the filmdiffers, for example, due to a film type formed at the semiconductorwafer, and heating distribution.

From this, for example, when the outer ring OUR1 is not formed, a cutsurface by the laser dicing is likely to be a concavo-convex shape dueto the difference in flammability of the film formed at thesemiconductor wafer. As a result of this, foreign substances (dust) areeasily generated from the concavo-convex shaped cut surface (refer toFIG. 6).

In contrast with this, in the present tenth embodiment, the outer ringOUR1 is arranged near the outer peripheral line of the ring region RR asshown in FIG. 40. As a result of this, as shown in FIG. 40, beforeflammability of the film formed at the semiconductor wafer is reflected,disappearance of the film stops outside the outer ring OUR1. Thereby, asshown in FIG. 40, the cut surface by the laser dicing has a uniformshape (flat shape) as compared with a case of FIG. 6 of not providingthe outer ring OUR1. From this, according to the present tenthembodiment, since the cut surface is smooth, generation of foreignsubstances (dust) can be reduced as compared with the case where the cutsurface has the concavo-convex shape.

As described above, in the present tenth embodiment, the outer ring OUR1is formed for the purpose of smoothing the cut surface by the laserdicing. In other words, it is conceived that unlike the case ofmechanical cutoff by the dicing blade, there is no generation of thecrack in the dicing step in the case of laser dicing. From this, asshown in FIG. 40, when premised on the laser dicing, even the grooveportion DIT is not provided in the surface protection film PAS, and, theouter ring OUR1 is formed so as to be as close as possible to the outerperipheral line of the ring region RR. Although such configuration ofthe tenth embodiment is the configuration premised on the laser dicing,in this case as well, reliability deterioration of the semiconductordevice due to generation of the foreign substances can be suppressed.

From the discussion described above, not only in the cases of mechanicalcutoff by the dicing blade as in the above-described First to ninthembodiments but in the case of being premised on the laser dicing as inthe present tenth embodiment, it can be seen that the configuration inwhich the outer ring OUR1 is provided in the ring region RR is a usefultechnical idea from a viewpoint of improving a quality of thesemiconductor device.

Hereinbefore, although the invention made by the present inventor hasbeen specifically explained based on the embodiments thereof, it isneedless to say that the present invention is not limited to theabove-described embodiments, and that various modifications can be madewithout departing from the gist of the invention.

The embodiments include the following aspects.

APPENDIX 1

A semiconductor device having a semiconductor chip,

the semiconductor chip including:

a circuit region in which an integrated circuit has been formed; and

a ring region formed outside the circuit region,

in which in the ring region, there are formed:

(a) a semiconductor substrate;

(b) a seal ring formed over the semiconductor substrate; and

(c) an outer ring formed outside the seal ring,

in which the seal ring is connected to the semiconductor substrate, and

in which the outer ring is arranged above a field insulating film formedon the semiconductor substrate, and is arranged spaced apart from thefield insulating film.

APPENDIX 2

The semiconductor device described in Appendix 1, in which a surfaceheight of the semiconductor substrate connected to the seal ring isdifferent from a surface height of the field insulating film locatedbelow the outer ring.

APPENDIX 3

The semiconductor device described in Appendix 1,

in which in the ring region, there are further formed:

(d) a surface protection film formed over the seal ring; and

(e) a groove portion formed in the surface protection film, the grooveportion being formed outside the seal ring, and

in which the outer ring is formed between the seal ring and the grooveportion.

APPENDIX 4

The semiconductor device described in Appendix 1,

in which the semiconductor chip has a corner, and

in which a first space between the seal ring and the outer ring in thecorner is larger than a second space between the seal ring and the outerring in a region other than the corner.

APPENDIX 5

The semiconductor device described in Appendix 4, in which a distancebetween an outer end of the ring region and the outer ring is smallerthan a distance between the outer ring and the seal ring.

APPENDIX 6

The semiconductor device described in Appendix 5, in which a width ofthe outer ring is smaller than a width of the seal ring.

APPENDIX 7

A semiconductor wafer having:

a plurality of chip regions; and

a scribe region that partitions the chip regions,

each of the chip regions including:

a circuit region in which an integrated circuit has been formed; and

a ring region formed outside the circuit region, and

the scribe region existing outside the ring region,

in which in the ring region, there are formed:

(a) a semiconductor substrate;

(b) a seal ring formed over the semiconductor substrate; and

(c) an outer ring formed outside the seal ring,

in which the seal ring is connected to the semiconductor substrate, and

in which the outer ring is arranged above a field insulating film formedon the semiconductor substrate, and is arranged spaced apart from thefield insulating film.

What is claimed is:
 1. A semiconductor device comprising: (a) asemiconductor substrate of quadrilateral shape having a pair of firstopposed edges and a pair of second opposed edges; (b) a seal ring formedover the semiconductor substrate so as to surround an integrated circuitforming region in plan view, the seal ring being formed of amulti-layered metal wirings; (c) first dummy patterns formed over thesemiconductor substrate which is positioned outside the seal ring inplan view, the first dummy patterns including a wiring layer formed ofthe same layer as a first one layer of the multi-layered metal wirings;and (d) second dummy patterns formed over the semiconductor substratewhich is positioned outside the seal ring in plan view, the second dummypatterns including a wiring layer formed of the same layer as a secondone layer of the multi-layered metal wirings, wherein the first dummypatterns are arranged along one of the pair of first opposed edges andone of the pair of second opposed edges, wherein the second dummypatterns are arranged at a corner portion defined by the one of the pairof first opposed edges and the one of the pair of second opposed edgesin plan view, wherein the first dummy patterns have square shape in planview, wherein the second dummy patterns have rectangular shape andextend in a direction intersecting the one of the pair of first opposededges and the one of the pair of second opposed edges in plan view, andwherein a long edge of each of the second dummy patterns is longer thanone edge of each of the first dummy patterns.
 2. A semiconductor deviceaccording to claim 1, wherein a short edge of each of the second dummypatterns is shorter than one edge of each of the first dummy patterns.3. A semiconductor device according to claim 1, wherein the first dummypatterns are arranged along the pair of first opposed edges and the pairof second opposed edges, and wherein the second dummy patterns arearranged at four corner portions defined by the pair of first opposededges and the pair of second opposed edges in plan view.
 4. Asemiconductor device according to claim 1, wherein the first and seconddummy patterns are not connected to the semiconductor substrate.
 5. Asemiconductor device according to claim 1, wherein an upper most wiringlayer is formed of the same layer as a pad, and wherein the first andsecond dummy patterns are formed of at least one of lower wiring layersthan the upper most wiring layer.
 6. A semiconductor device according toclaim 1, wherein the first dummy patterns includes wiring layers formedof the same layers as first adjacent layers of the multi-layered metalwirings respectively, the first adjacent layers being not connected toeach other through plugs, and wherein the second dummy patterns includeswiring layers formed of the same layers as second adjacent layers of themulti-layered metal wirings respectively, the second adjacent layersbeing connected to each other through plugs.